Shuffle Exchange Research Articles

Replicated multistage interconnection networks: QoS evaluation for parallel and distributed computing

Introduction to big data becomes very important with dealing in high-performance parallel distributed computing, especially in those systems where communication among a number of processors is required. The current paper takes into consideration different topologies for the Shuffle Exchange Network (SEN) in order to attain optimal data transfer among such scenarios. SEN topologies are a key feature in connecting several processors and implementing the data transfer among them where a single processor fails to handle the load. The study hereby reports in the performance, reliability, and cost analysis of these topologies. These topologies, some of which are advocated to have better performance in many studies, include replicated networks. Our research demystifies claims made in earlier papers that replicated networks have inflated reliability and higher costs due to their additional links. Researchers are therefore guided on accurate performance data that will lead them to make optimum choices of SEN topologies for targeted applications. These findings further highlight that the trade-offs between reliability and cost must be carefully considered during network design so as to arrive at better results for big data communication and computation in parallel and distributed systems. This work provides important insights into the correct evaluation of SEN topologies, helping to correct the misleading facts and to have better network selection for various real-time application realizations.

Publisher Correction to: On design and performance analysis of improved shuffle exchange gamma interconnection network layouts

Publisher Correction to: On design and performance analysis of improved shuffle exchange gamma interconnection network layouts

Publisher Correction: On design and performance analysis of improved shuffle exchange gamma interconnection network layouts

Publisher Correction: On design and performance analysis of improved shuffle exchange gamma interconnection network layouts

On design and performance analysis of improved shuffle exchange gamma interconnection network layouts

On design and performance analysis of improved shuffle exchange gamma interconnection network layouts

A matheuristic approach for the minimum broadcast time problem using a biased random‐key genetic algorithm

AbstractThe Minimum Broadcast Time (MBT) is a well‐known data dissemination problem whose goal is to find a broadcast scheme that minimizes the number of steps needed to execute the broadcast operation. The problem has many applications in distributed systems and, in particular, the Industry 4.0 domain. Because Industry 4.0 applications rely primarily on the use of large‐scale machine to machine communications, they need data dissemination techniques that combine high reliability with low communication latency. This work proposes a Biased Random‐Key Genetic Algorithm and a matheuristic for the MBT. We carry out experiments with our algorithms on instances commonly used in the literature (hypercube, shuffle exchange, cube‐connected cycles, de Bruijn, Harary graphs), and also on massive synthetic instances (up to 1000 vertices), allowing to cover many possibilities of real industry topologies. Our proposal is also compared with state‐of‐the‐art exact methods and heuristics. Experimental results show that our algorithm is able to outperform the best‐known heuristics for the MBT, and also that it is a very good alternative for large instances that cannot be solved by current exact methods.

A 3-disjoint path design of non-blocking shuffle exchange network by extra port alignment

A 3-disjoint path design of non-blocking shuffle exchange network by extra port alignment

Reliability Estimation of 4 × 4 SENs Using UGF Method

Shuffle Exchange Networks (SENs) are considered as an appropriate interconnection network because they consist of switching elements of small size and possess a straight forward and simple configuration. In this paper, we have proposed a method for analyzing reliability of 4×4 SEN, 4×4 SEN+1 and 4×4 SEN+2. The reliability has been obtained on the basis of three indices, namely, terminal reliability, broadcast reliability and network reliability by using universal generating function (UGF) method. This study also examines effect of adding the additional stages in 4×4 shuffle exchange networks (SENs).

A Primer on Design Aspects and Recent Advances in Shuffle Exchange Multistage Interconnection Networks

Interconnection networks provide an effective means by which components of a system such as processors and memory modules communicate to provide reliable connectivity. This facilitates the realization of a highly efficient network design suitable for computational-intensive applications. Particularly, the use of multistage interconnection networks has unique advantages as the addition of extra stages helps to improve the network performance. However, this comes with challenges and trade-offs, which motivates researchers to explore various design options and architectural models to improve on its performance. A particular class of these networks is shuffle exchange network (SEN) which involves a symmetric N-input and N-output architecture built in stages of N/2 switching elements each. This paper presents recent advances in multistage interconnection networks with emphasis on SENs while discussing pertinent issues related to its design aspects, and taking lessons from the past and current literature. To achieve this objective, applications, motivating factors, architectures, shuffle exchange networks, and some of the performance evaluation techniques as well as their merits and demerits are discussed. Then, to capture the latest research trends in this area not covered in contemporary literature, this paper reviews very recent advancements in shuffle exchange multistage interconnection networks within the last few years and provides design guidelines as well as recommendations for future consideration.

SEGIN-Minus: A New Approach to Design Reliable and Fault-Tolerant MIN

Background:VLSI technology advancements have resulted the requirements of high computational power, which can be achieved by implementing multiple processors in parallel. These multiple processors have to communicate with their memory modules by using Interconnection Networks (IN). Multistage Interconnection Networks (MIN) are used as IN, as they provide efficient computing with low cost.Objective:the objective of the study is to introduce new reliable MIN named as a (Shuffle Exchange Gamma Interconnection Network Minus) SEGIN-Minus, which provide reliability and faulttolerance with less number of stages.Methods:MUX at input terminal and DEMUX at output terminal of SEGIN has been employed with reduction in one intermidiate stage. Fault tolerance has been introduced in the form of disjoint paths formed between each source-destnation node pair. Hence reliability has been improved.Results:Terminal, Broadcast and Network Reliability has been evaluated by using Reliability Block Diagrams for each source-destination node pair. The results have been shown, which depicts the hiher reliability values for newly proposed network. The cost analysis shows that new SEGINMinus is a cheaper network than SEGIN.Conclusion:SEGIN-Minus has better reliability and Fault-tolerance than priviously proposed SEGIN.

Game chromatic number of some network graphs

In this paper, we determine the exact values of the game chromatic number of some interconnection network graph families such as shuffle exchange network, cube-connected cycles and wrapped around butterflies

Mean Time to Failure Analysis in Shuffle Exchange Systems

Multistage Interconnection Network (MIN) has been researched for the interconnection implementation of switches and multiprocessors. The topology of the interconnection, the number of stage and the switching element used in the network distinguish between each MIN's tolerance of failure.This paper introduces a topology called Replicated Shuffle Exchange Network and Replicated Augmented Shuffle Exchange Network. A replicated technique is described for making the network more reliable. The replicated technique results in reduced the Mean Time to Failure in the network. Performance measurement shows that replicated network achieve a significant improvement over a basic network have been measured.

Design and reliability analysis of fault-tolerant shuffle exchange gamma logical neighborhood interconnection network

Multistage interconnection networks are used as a medium for interconnecting processors and memories in multiprocessor systems. Multistage interconnection networks are an effective substitute for crossbar switches, used in telephone network systems and parallel computers, due to their low cost, better performance and easy maintainability. In this paper, we propose new fault-tolerant hybrid multistage interconnection networks obtained from shuffle exchange gamma interconnection network (SEGIN) and logical neighborhood network named as shuffle exchange gamma logical neighborhood interconnection network (SEGLNIN). We evaluated the performance of SEGLNIN in terms of disjoint paths, reliability and hardware cost and compared it with some well-known MINs like shuffle exchange network (SEN), shuffle exchange network with one extra stage (SEN +) and shuffle exchange network with two extra stages (SEN + 2), SEGIN-1, and SEGIN-2. The results illustrate that the performance of the proposed SEGLNIN is better than that of the compared networks in terms of reliability and disjoint paths.

Integrating Replicated Network in Reliability Shuffle Exchange Network System

Integrating Replicated Network in Reliability Shuffle Exchange Network System

Design of Fault Tolerant Shuffle Exchange Gamma Interconnection Network Layouts

Advancement in technology has resulted in increased computing power with the use of multiple processors within a system. These multiple processors need to communicate with each other and with memory modules. Multistage Interconnection Networks (MINs) provide a communication medium in such multi-processor systems by interconnecting a number of processors and memory modules. Besides, MINs also provide a cost effective substitute to costly crossbars in parallel computers and switching systems in telephone industry. This paper introduces two new fault-tolerant MINs named as Shuffle Exchange Gamma Interconnection Networks (SEGIN-1 and SEGIN-2). SEGIN-1 and SEGIN-2 can be obtained by altering Shuffle Exchange Network with one extra stage (SEN+) and provide two disjoint paths similar to it. Performance of SEGIN-1 and SEGIN-2 has been evaluated in terms of alternative paths, disjoint paths, reliability and hardware cost, and is compared with some very famous MINs like Shuffle Exchange Network (SEN), Shuffle Exchange Network with one extra stage (SEN+), Shuffle Exchange Network with two extra stage (SEN+2), Extra Stage Cube (ESC) and Gamma Interconnection Network (GIN). Results suggest that SEGINs surpass all the compared networks; hence, the proposed designs seem to be suitable for implementing practical interconnection networks.

A New SEN Minus: Design and Reliability Measures

Multistage interconnection networks (MIN) are becoming attractive choice as they provide fast and efficient communication at reasonable cost, for multiprocessing systems. Shuffle exchange network (SEN) are specific class of MIN characterized as lowest cost unipath MIN. Several developments have made SEN MIN fault tolerant with redundant paths by increasing the number or size of switching elements (SE). However, recently [Formula: see text] has been advanced by reducing the number of stages, but has serious limitation namely: (i) partial connectivity of each source–destination pair, (ii) unique path. A new method has been proposed in this paper to develop a new topology of MIN with one stage less than the basic unipath MIN of same class with multiple and disjoint path facility that mitigates the shortcomings of the above network and is truly [Formula: see text] MIN. Due to less number of stages used in the proposed network communication delays are also reduced as the path length is reduced. Parametric performances such as Terminal, Broadcast and Network Reliabilities, MTTF, Bandwidth have been computed for different network sizes and demonstrated that it not only outperforms other SEN variants, but has improved features of fault tolerance all because of disjoint minimal path set. Further the comments generated previously in literature about better reliability performance of [Formula: see text] than other two networks [Formula: see text] have been refuted and have demonstrated that [Formula: see text]2 network has better performance than other two for larger network size. Also it can be concluded that the performance of proposed [Formula: see text] is best among all these networks.

Поддержка стандарта OpenMP 4.0 для архитектуры NVIDIA PTX в компиляторе GCC

The paper describes the approach used in implementing OpenMP offloading to NVIDIA accelerators in GCC. Offloading refers to a new capability in OpenMP 4.0 specification update that allows the programmer to specify regions of code that should be executed on an accelerator device that potentially has its own memory space and has an architecture tuned towards highly parallel execution. NVIDIA provides a specification of the abstract PTX architecture for the purpose of low-level, and yet portable, programming of their GPU accelerators. PTX code usually does not use explicit vector (SIMD) computation; instead, vector parallelism is expressed via SIMT (single instruction - multiple threads) execution, where groups of 32 threads are executed in lockstep fashion, with support on hardware level for divergent branching. However, some control flow constructs such as spinlock acquisition can lead to deadlocks, since reconvergence points after branches are inserted implicitly. Thus, our implementation maps logical OpenMP threads to PTX warps (synchronous groups of 32 threads). Individual PTX execution contexts are therefore mapped to logical OpenMP SIMD lanes (this is similar to the mapping used in OpenACC). To implement execution of one logical OpenMP thread by a group of PTX threads we developed a new code generation model that allows to keep all PTX threads active, have their local state (register contents) mirrored, and have side effects from atomic instructions and system calls such as malloc happen only once per warp. This is achieved by executing the original atomic or call instruction under a predicate, and then propagating the register holding the result using the shuffle exchange (shfl) instruction. Furthermore, it is possible to setup the predicate and the source lane index in the shuffle instruction in a way that this sequence has the same effect as just the original instruction inside of SIMD regions. We also describe our implementation of compiler-defined per-warp stacks, which is required to have per-warp automatic storage outside of SIMD regions that allows cross-warp references (normally automatic storage in PTX is implemented via .local memory space which is visible only in the PTX thread that owns it). This is motivated by our use of unmodified OpenMP lowering in GCC where possible, and thus using libgomp routines for entering parallel regions, distribution of loop iterations, etc. We tested our implementation on a set of micro-benchmarks, and observed that there is a fixed overhead of about 100 microseconds when entering a target region, mostly due to startup procedures in libgomp (and notably due to calls to malloc), but for long-running regions where that overhead is small we achieve performance similar to analogous OpenACC and CUDA code.

Reliability Evaluation for Shuffle Exchange Interconnection Network

Abstract Shuffle-exchange networks (SENs) have been generally considered as a convenient interconnection systems due to the size of their switching elements (SEs) and simple configuration. Evaluation of reliability performance has been attempted by researchers in the past. This paper is a depth study of reliability evaluation in shuffle exchange network. We propose a SEN with minus one stage (SEN-) and compared with three other types of SEN. The measurement includes three parameters; terminal, broadcast and network reliability.

English

The reliability can be measured in terms of MTTF i.e. Mean Time To Failure. It is defined as expected time elapsed before some source is disconnected from some destination. In this paper Optimistic and Pessimistic MTTF Bounds of proposed Multistage Interconnection Network (MIN) New Irregular Augmented Shuffle Exchange Network (NIASN) have been evaluated and compared with existing similar class of MINs Augmented Baseline Network (ABN).

Shuffle Exchange Networks and Achromatic Labeling

Design of interconnection networks is an important integral part of the parallel processing or distributed systems. There are a large number of topological choices for interconnection networks. Among several choices, the Shuffle Exchange Network is one of the most popular versatile and efficient topological structures of interconnection networks. In this paper, we have given a new method of drawing shuffle exchange network for any dimension. This has enabled us to investigate some of the topological properties of shuffleexchange network.

Reliability Evaluation and Routing Integration in Shuffle Exchange Omega Network

Multistage Interconnection Networks (MINs) are design to provide an effective communication in switching. Shuffle-exchange networks (SENs) have been widely considered as practical interconnection systems due to their size of it switching elements (SEs) and uncomplicated configuration. In this paper, the relationship between reliability performance and number of network size are compared in shuffle exchange network (SEN) and SEN with minus one stages (SEN-). There are three parameters used to measure the reliability performance on these networks which is terminal reliability, broadcast reliability and network reliability. An addition this paper also focused on comparing the algorithm based on SEN- to achieve the optimal routing time and the number of passes. The algorithms consist of six algorithms namely ZeroX, ZeroY, ZeroXbit, ZeroYbit, Sequential Increasing and Sequential Decreasing algorithm. This paper also shows the details of the illustrative examples used to explain each parameter measures. At the end of this chapter, the comparative analysis shows the performance of each parameters measures.