Short-circuit Program Research Articles

Evaluating Generator Circuit Breakers Short-Circuit Duty Using IEEE C37.010 and C37.013

This paper describes a procedure for calculating generator circuit breaker duty. Currently, commercially available software products help in determining the duty for a general-purpose circuit breaker. However, further calculations are needed to determine the duty for a special-purpose generator circuit breaker. IEEE Std C37.010-1999 provides the calculation procedure for general-purpose circuit breakers. In order to evaluate a special-purpose generator circuit breaker, this paper will expand the steps and methodology used in IEEE C37.010-1999 by presenting a procedure and detailed calculations for finding a duty multiplication factor based on the test X/R ratio of generator circuit breakers given in IEEE C37.013-1997 (Standard for AC High-Voltage Generator Circuit Breakers Rated on a Symmetrical Current Basis). This way, engineers can still make a generator circuit breaker assessment although generator circuit breaker evaluation module is not included in many commercial short-circuit programs.

Validation of Voltage Sag Simulation Tools: ATP and Short-Circuit Calculation Versus Field Measurements

Two methods to calculate voltage sags are validated against actual measurements. One of the methods is a short-circuit calculation program resulting directly in sag magnitude during the fault. The other is an electromagnetic transient program resulting in voltage waveform as a function of time. Individual sag characteristics and system performance obtained by deterministic simulation and measurement are compared. The influence of the random variables (prefault voltage, fault location and fault impedance) is investigated.

Sparse Computation of Power System Fault Impedance Matrices

This paper presents a contribution that enhances the efficiency of sparsity techniques for solving some problems in large-scale power systems. Alterations are introduced on storage schemes and node ordering to lead to a reduction of the computation time and space memory. The fast sparse vector approach (FSV) is presented and implemented in a short circuit program to compute fault currents and fault bus voltages. It is based on a formulation that computes only the required column of the Z impedance matrix (or some elements of the column) for any particular type of fault. The tests carried out on several power systems ranging from the IEEE 30 bus to a 1084 bus test system show that the proposed approach gives an important reduction of computation time.

Systematized short-circuit analysis of a 2×25 kV electric traction network

Abstract This paper presents a systematic approach for short-circuit analysis of a 2×25 kV electric railway system. This approach uses a full-scale model of a 2×25 kV electric traction network. The model is composed of a substation model, autotransformer (AT) models, and network conductor models. The substation model considers the three most commonly used connection schemes of traction transformers. There are single-phase, V and Scott connections. The AT model considers the impedance and inherent characteristics of the AT, while the network conductor model considers the self and mutual impedances of three major conductors in a traction network (overhead contact wire, return feeder and rail). These models are all in coupling-free type. Therefore they can be easily implemented into a self-developing program or commercial packages, such as a short-circuit program in phase coordinates, the Electromagnetic Transients Program (EMTP), or the Personal Computer Simulation Program with Integrated-Circuit Emphasis (PSPICE). With the proposed models, a short-circuit analysis program is developed by the node admittance matrix method. In this manner, the fault currents in each branch in a traction network as well as the curves of fault currents versus fault location can be easily achieved. Furthermore, the voltages at the overhead contact wire and return feeder along a railway route can be calculated if required.

Transformer and load modeling in short circuit analysis for distribution systems

Accuracy of short circuit analysis depends on the modeling of transformers and loads. This paper addresses implementation of various transformer and load models in a short-circuit analysis for three-phase unbalanced distribution systems. Detailed transformer models are derived and incorporated into a production grade short circuit program with three different load models. Our studies show that different transformer connections, load models, and loading conditions may have significant impact on post-fault currents and voltages. Some test results on PG&E distribution feeders are presented.

A distribution short circuit analysis approach using hybrid compensation method

This paper addresses a new approach for real-time short circuit analysis of radial and weakly meshed distribution networks. The approach works based on a well documented radial power flow study method, and uses a hybrid compensation method to account for loops, PV nodes, and fault currents simultaneously. The three-phase short circuit analysis, in its actual a-b-c phase representation, can be applied to balanced or unbalanced distribution systems. A distribution short circuit program which is developed based on this approach, is integrated with a three-phase power flow program to solve various types of single or simultaneous faults, including single-line to ground, three-line to ground, double-line to ground, line-to-line, and double three-line to ground faults. Results of the application of this approach to large-scale distribution networks are also reported in this paper.

Superposition technique for MOV-protected series capacitors in short-circuit calculations

A new method for modeling series capacitors protected by metal oxide varistors is developed using superposition on sequence networks. This technique is incorporated in a short-circuit program within an iterative process which allows the consideration of the nonlinear characteristic of metal oxide varistor (MOV) protected series capacitors. The iterative process is rendered dynamic by evaluating the voltage and current of the series capacitors and by adjusting the state of the varistors at each iteration without reformulating the network nodal admittance matrix. The 60 Hz impedance characteristic of the nonlinear MOV protected series capacitors is simulated by fictive shunt current sources across varistors. Results show that the proposed procedure can adequately and efficiently model MOV protected series capacitors in a standard short-circuit program.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Modeling MOV-protected series capacitors for short-circuit studies

A procedure for adequately modeling series capacitors protected by metal oxide varistor (MOV) in a conventional short-circuit program is proposed. It uses a quasi-linear model to represent the nonlinear characteristic of the MOVs, combined with a compensation technique to represent the intersequence coupling during unbalanced faults. The effectiveness of the method, which is valid for unbalanced as well as balanced faults, is demonstrated by comparing the results with those obtained using time-domain simulations. The results show that the proposed procedure can adequately and efficiently model MOV-protected series capacitors in a standard short-circuit program.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Sparsity-enhanced network reduction for fault studies

A new short-circuit equivalent and reduction program is described that uses the adaptive reduction technique in which extra path nodes are retained to produce a sparser equivalent network. Nodes that may be reduced are chosen by flexible set formation facilities, with path nodes automatically retained as required to preserve sparsity. Tests on typical systems show that the sparsity-enhanced reduction produces an equivalent with fewer branches and a much lower branch-to-node ratio than conventional reduction for a wide range of numbers of nodes eliminated. At some point, as the number of retained nodes becomes small, conventional reduction produces an equivalent with fewer branches. >

Sample system for three-phase short circuit calculations

The development of short-circuit programs and their use on nuclear electric power systems require that the program results be compared against hand calculations or another proven program. A comparison is given of the results of different types of network solutions for a sample one-line diagram and the corresponding data. The purpose is to provide a sample short-circuit program input-output and a range of solution variance for different numerical methods currently being used by contributors of alternate solutions.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

On-line, parallel short-circuit calculations

It is suggested that instead of scheduling faultcalculations offline, one-by-one, they should be submitted as a basic case followed by a number of slightly changed cases. All should be done on-line, preferably on an “Alternating Sequential/Parallel” (ASP) system.—Section 1 introduces the idea of using updating and diakoptics for running short-circuit programs on-line, on ASP. Section 2 discusses how the recursive calculation of the bus-impedance matrix can be parallelized. Section 3 develops a program for the parallel solution using “diakoptics”. It can be scheduled so that a number of different righthand sides (currents) are computed concurrently. Section 4 shows how to update the solution vector (normally both currents and voltages) when line impedances are changed.

A Complete 500-Bus Short Circuit Program for Use with a Small Computer

A short circuit program using the Z bus matrix which can be executed for a 500-bus system on a 16K, two byte word computer is described. A star-mesh reduction routine automatically reduces the network ork a sufficient number of times to permit formation of matrices which are compatible with the smaller computer.

Simultaneous Solution of Line-Out and Open-End Line-to-Ground Short Circuits

One prime objective in developing a computer program is to minimize the running time requirements. For short-circuit programs, one major obstacle is the time absorbed in processing mutually coupled elements for line-out and open-end conditions.