Shared-memory Symmetric Multiprocessor Research Articles

Scalable shot boundary detection

In a Content-based Video Retrieval system, the shot boundary detection is an unavoidable stage. Such a high demanding task needs a deep study from a computational point of view to allow finding suitable optimization strategies. This paper presents different strategies implemented on both a shared-memory symmetric multiprocessor and a Beowulf cluster, and the evaluation of two different programming paradigms: shared-memory and message passing. Several approaches for video segmentation as well as data access are tested in the experiments that also consider load balancing issues.

A real-time Java chip-multiprocessor

Chip-multiprocessors are an emerging trend for embedded systems. In this article, we introduce a real-time Java multiprocessor called JopCMP. It is a symmetric shared-memory multiprocessor, and consists of up to eight Java Optimized Processor (JOP) cores, an arbitration control device, and a shared memory. All components are interconnected via a system on chip bus. The arbiter synchronizes the access of multiple CPUs to the shared main memory. In this article, three different arbitration policies are presented, evaluated, and compared with respect to their real-time and average-case performance: a fixed priority, a fair-based, and a time-sliced arbiter. Tasks running on different CPUs of a chip-multiprocessor (CMP) influence each others' execution times when accessing a shared memory. Therefore, the system needs an arbiter that is able to limit the worst-case execution time of a task running on a CPU, even though tasks executing simultaneously on other CPUs access the main memory. Our research shows that timing analysis is in fact possible for homogeneous multiprocessor systems with a shared memory. The timing analysis of tasks, executing on the CMP using time-sliced memory arbitration, leads to viable worst-case execution time bounds. The time-sliced arbiter divides the memory access time into equal time slots, one time slot for each CPU. This memory arbitration scheme allows for a calculation of upper bounds of Java application worst-case execution times, depending on the number of CPUs, the time slot size, and the memory access time. Examples of worst-case execution time calculation are presented, and the analyzed results of a real-world application task are compared to measured execution time results. Finally, we evaluate the tradeoffs when using a time-predictable solution compared to using average-case optimized chip-multiprocessors, applying three different benchmarks. These experiments are carried out by executing the programs on the CMP prototype.

Software-Based Self-Testing of Symmetric Shared-Memory Multiprocessors

Software-based or instruction-based self-testing has recently emerged as an effective alternative for the manufacturing and online testing of microprocessors, and is progressively adopted by major microprocessor manufacturers mainly as a supplement to other mature and well-established testing approaches to reach higher test quality. Thus far, software-based self-test approaches presented in the literature have focused almost exclusively on uniprocessors. With the continuing prevalence of multiprocessors, the focus of such research approaches moves from the uniprocessor to the multiprocessor case. In this paper, we study the application of software-based self-testing on symmetric shared-memory multiprocessors (SMP) considering the most common interconnection architectures, shared bus and crossbar switch. We focus on the impact of the shared-memory system architecture, the cache coherence mechanisms, and the interconnection architecture on the execution time of self-test programs running on each separate core and exploit the SMP's parallelism during testing to reduce the test execution time. We propose a generic methodology that allocates the test programs and test responses into the shared on-chip memory and schedules the test routines among the cores aiming at the reduction of the total test application time, and thus, test cost, for the SMP, by increasing the execution parallelism and reducing both bus contentions and data cache invalidations. We demonstrate the proposed solutions with detailed experiments on several two-core, four-core, and eight-core SMP benchmarks based on a popular RISC benchmark processor using both the shared bus and the crossbar switch interconnection architectures.

Parallel parsing of MPEG video on a shared-memory symmetric multiprocessor

Video parsing refers to the detection and classification of abrupt and gradual scene changes in a video stream. The detection of these changes forms an important preprocessing step in applications that treat videos as sources of information. The parsed video is subsequently indexed to support content-based retrieval, navigation and browsing. Analysis of video streams is computationally intensive with high data processing bandwidth requirements. Shared-memory symmetric multiprocessors (SMPs) have become increasingly ubiquitous and affordable. Parallel processing on an shared-memory symmetric multiprocessor is hence proposed as a means of dealing with the computational demands of video parsing. Parallel versions of two algorithms that detect scene transitions in compressed video streams are proposed. Both algorithms entail minimal decompression of the MPEG video. Three granularities of parallelism based on data decomposition and task decomposition are investigated; Group of Pictures (GOP), Frame and Slice. Results of an SMP implementation show that the GOP-level implementation, which represents the coarsest granularity of task and data decomposition, performs the best in terms of speedup and synchronization overhead. The slice and frame levels of granularity take second and third place, respectively. The speedup is observed to be almost linear in the case of the GOP level of granularity, whereas the synchronization overheads are observed to be high for the frame and slice levels of granularity.

Parallel iterative solvers for unstructured grids using a directive/MPI hybrid programming model for the GeoFEM platform on SMP cluster architectures

AbstractIn this paper, an efficient parallel iterative method for unstructured grids developed by the authors for shared memory symmetric multiprocessor (SMP) cluster architectures on the GeoFEM platform is presented. The method is based on a three‐level hybrid parallel programming model, including message passing for inter‐SMP node communication, loop directives for intra‐SMP node parallelization and vectorization for each processing element (PE). Simple 3D elastic linear problems with more than $10^8$ degrees of freedom have been solved by $3\times3$ block ICCG(0) with additive Schwarz domain decomposition and PDJDS/CM‐RCM reordering on 16 SMP nodes of a Hitachi SR8000 parallel computer, achieving a performance of 20 Gflops. The PDJDS/CM‐RCM reordering method provides excellent vector and parallel performance in SMP nodes, and is essential for parallelization of forward/backward substitution in IC/ILU factorization with global data dependency. The method developed was also tested on an NEC SX‐4 and attained 969 Mflops (48.5% of peak performance) using a single processor. The additive Schwarz domain decomposition method provides robustness for the GeoFEM parallel iterative solvers with localized preconditioning. Copyright © 2002 John Wiley & Sons, Ltd.

Implementation of distributed iterative algorithm for optimal control problems on several parallel architectures

We consider an optimal control problem without constraint. The solution of this problem leads to a large scale block linear system. We present a two-stage method which is well suited to an asynchronous implementation with flexible communication whereby every processor can have access at any time and without any fixed rule to the current value of the components of the iteration vector updated by any other processor. The implementation is carried out on three types of architecture: a super computer with distributed memory CRAY T3E, a shared memory symmetric multiprocessor (SMP) and a high speed network of SMP.

A Real-Time North American Forecast at 10-km Resolution with the Canadian MC2 Meso-LAM

Abstract The next generation of high-performance computers will be based on clusters of shared-memory symmetric multiprocessor (SMP) nodes interconnected by a low-latency, high-bandwidth network. In this paper, the parallel performance of the nonhydrostatic Mesoscale Compressible Community (MC2) limited-area atmospheric model on clusters of NEC SX-4 symmetric multiprocessor (SMP) nodes is presented. Several hybrid parallel-programming approaches are now possible with the SMP cluster SC-MC2 implementation based on internode MPI message-passing and intranode shared-memory tasking or threads. At total sustained execution rates of between 25 and 30 Gflop s−1 on single-node or multinode clusters, it is now possible for the first time ever to generate a 24–48-h real-time weather forecast over North America at 10-km resolution.