Shared Memory Pool Research Articles

MOSIQS: Persistent Memory Object Storage With Metadata Indexing and Querying for Scientific Computing

Scientific applications often require high-bandwidth shared storage to perform joint simulations and collaborative data analytics. Shared memory pools provide a chance to satisfy such needs. Recently, a high-speed network such as Gen-Z utilizing persistent memory (PM) offers an opportunity to create a shared memory pool connected to compute nodes. However, there are several challenges to use scientific applications on the shared memory pool directly such as scalability, failure-atomicity, and lack of scientific metadata-based search and query. In this paper, we propose MOSIQS, a persistent memory object storage framework with metadata indexing and querying for scientific computing. We design MOSIQS based on the key idea that memory objects on PM pool can live beyond the application lifetime and can become the sharing currency for applications and scientists. MOSIQS provides an aggregate memory pool atop an array of persistent memory devices to store and access memory objects to accelerate scientific computing. MOSIQS uses a lightweight persistent memory key-value store to manage the metadata of memory objects, which enables memory object sharing. To facilitate metadata search and query over millions of memory objects resident on memory pool, we introduce Group Split and Merge (GSM), a novel persistent index data structure designed primarily for scientific datasets. GSM splits and merges dynamically to minimize the query search space and maintains low query processing time while overcoming the index storage overhead. MOSIQS is implemented on top of PMDK. We evaluate the proposed approach on many-core server with an array of real PM devices. Experimental results show that MOSIQS gains a 100% write performance improvement and executes multi-attribute queries efficiently with 2.7× less index storage overhead offering significant potential to speed up scientific computing applications.

Caching Techniques for Security Metadata in Integrity-Protected Fabric-Attached Memories

The constant need for larger memories and the diversity of workloads have driving the system vendors away from the conventional processor-centric architecture into a memory-centric architecture. Memorycentric architecture, allows multiple computing nodes to connect to a huge shared memory pool and

Software Design for High-Speed Data Capture

10G Ethernet technology has been widely used in modern high speed communication system. As a result, program design for high-speed data capture on 10G Ethernet, as the first and important step in network monitor and analysis system, has become a challenging task. This paper proposed a high-speed data capture method based on WinCap and shared memory pool technology and has features of high speed, low packet loss rate, high efficiency and good portability. The system test and data analysis proved that the proposed method in this paper can effectively capture the data at speed of 6Gbps and stably keep the packet loss rate under 0.03%.

Redesigning MPI shared memory communication for large multi-core architecture

Modern multi-core platforms are evolving very rapidly with 32/64 cores for node. Sharing of system resource can increase communication efficiency between processes on the same node. However, it also increases contention for system resource. Currently, most MPI libraries are developed for systems with relatively small number of cores per node. On the emerging multi-core systems with hundreds of cores per node, existing shared memory mechanisms for MPI run-times will suffer from scalability problem, which may limit the benefits gained from multi-core system. In this paper, we first analyze these problems and then propose a set of new schemes for small message and large message transfer over shared memory. "Shared Tail Cyclic Buffer" scheme is proposed to reduce the number of read and write operations over shared control structures. "State-Driven Polling" scheme is proposed to optimize the message polling through dynamically adjusted polling frequency on different communication pairs. Through dynamic distribution of runtime pinned-down memory, "On-Demand Global Shared Memory Pool" is proposed to bring benefits of pair-wise buffer to large message transfer and optimize shared send buffer utilization without increasing the total shared memory usage. With micro-benchmark evaluation, the new schemes can bring up to 26 % and 70 % improvement for point-to-point latency and bandwidth performance, respectively. For applications, the new schemes can achieve 18 % improvement on the 64-core/node Bulldozer system for Graph500 benchmark, and up to 11 % improvement for NAS benchmarks. With 512 processes evaluation on 32-core Trestles system, the new schemes achieves 16 % improvement for NAS CG benchmark.

Reducing memory requirements in a multimedia streaming application

This paper investigates memory management for real-time multimedia applications running on resource-constrained electronic devices. The target applications are comprised of a data-driven task chain with a time-driven head and tail and a bounded end-to-end latency. The necessary buffer capacities along the task chain are derived. Subsequently it is shown how a shared memory pool can reduce the total memory requirements of the whole application. The impact of a shared memory pool is also evaluated in the context of scalable applications. The general technique targeted at memory-constrained streaming systems is demonstrated with a video encoding example, showing memory savings of about 19%.

Improving Response Time of Authorization Process of Credit Card System Using Multi-Threading and Shared-Memory Pool Techniques

Current credit card authorization was developed on single-threaded model whereby authentication process takes longer time to respond due to sequential process of card's risk management profile and its limitation of handling huge number of simultaneous transactions at single point of time. As a result, the performance of the authorization system was affected during peak hours. This study presented an architectural framework and prototype of credit card authorization system using multi-threading and shared memory pool techniques in order to improve the response time during authorization process. Through multi-threading technique, each worker thread will be assigned with several child threads to perform online fraud validation concurrently, depending on numbers of cryptographic elements presented in transaction message. Meanwhile, the worker threads itself performed card restriction validation based on the information stored in card's shared memory pool. This approach was implemented to reduce the idle time while waiting for slow cryptographic operation in each I/O operations that is performed through external device and to accelerate the authorization process through memory operation instead of accessing similar information from database. The implementation of these techniques, were then measured in terms of response time. The results showed that the performance of multi-threaded authentication engine was almost double of single-threaded authentication engine and the number of credit card authorization that can be processed using shared memory was ten percent higher than the number of credit card authorization that can be processed using database at single point of time.

Multiprocessor architecture to handle TJ-II VXI-based digitization channels

The data acquisition System (DAS) of the TJ-II stellerator provides up to 300 digitization channels integrated in register-based VXI modules designed in CIEMAT Laboratories. The modules are embedded into six 13-slot VXI chassis connected to the TJ-II DAS central computer by means of a dual LAN topology. During normal operation, remote control of the VXI systems and channel setup are accomplished through an Ethernet LAN, while two FDDI rings are dedicated to postdischarge fast data transfer. The former network link is performed by the bus controller whereas the latter one is provided through a FDDI node controller installed in the mainframe, thus creating a multiprocessor architecture. Dedicated software, running on the VxWorks operating system, has been developed to provide handling of the VXI systems including the following facilities: mainframe information readout, channel setup, real time digitization handling, and data transfer. This software, implemented in C++, is distributed over the two CPUs. Interprocessor communication for synchronization purposes is based on a backplane shared memory pool.