Shared-memory Multicore Platforms Research Articles

Optimizing Speedup on Multicore Platform with OpenMP Schedule Clause and Chunk Size

Despite the description of schedule type which can be easily found at any OpenMP reference material, little is known about the effect of different schedule type and chunk size on the parallel performance of shared memory multicore processor. Literature shows that performance analysis on different multicore platform overlooked the effect of different schedule type and chunk size, where often it was not explicitly specified. Hence, default assignment of the loop iterations among threads is assumed. By default, static schedule is used and size of chunk which is the ratio of total number of iteration to the number of threads is implemented. This research analyses the effect of different schedule type and chunk size on speedup achieved of different shared memory multicore platform under regular workload. Apart from that, the performance gain obtained after turning on/off certain multicore technologies and after turning on/off selected number of active cores per processor is also analysed. Results shows that different multicore technology exhibit different speedup value under different combination of schedule type and chunk size. Apart from that, it also observe that different multicore platform is better than the other in terms of speedup as the number of cores are increased.

TTADF: Power Efficient Dataflow-Based Multicore Co-Design Flow

The era of mobile communications and the Internet of Things (IoT) has introduced numerous challenges for mobile processing platforms that are responsible for increasingly complex signal processing tasks from different application domains. In recent years, the power efficiency of computing has been improved by adding more parallelism and workload-specific computing resources to such platforms. However, programming of parallel systems can be time-consuming and challenging if only low-level programming methods are used. This work presents a dataflow-based co-design framework TTADF that reduces the design effort of both software and hardware design for mobile processing platforms. The paper presents three application examples from the fields of video coding, machine vision, and wireless communications. The application examples are mapped and profiled both on a pipelined and a shared-memory multicore platform that is generated by TTADF. The results of the TTADF co-design-based solutions are compared against previous manually created designs and a recent dataflow-based design flow, showing that TTADF provides very high energy efficiency together with a high level of automation in software and hardware design.

Block coordinate descentwith time perturbation for nonconvex nonsmooth problems in real-world studies

The era of big data in healthcare is here, and this era will significantly improve medicine and especially oncology. However, traditional machine learning algorithms need to be promoted to solve such large-scale realworld problems due to a large amount of data that needs to be analyzed and the difficulty in solving problems with nonconvex nonlinear settings. We aim to minimize the composite of a smooth nonlinear function and a block-separable nonconvex function on a large number of block variables with inequality constraints. We propose a novel parallel first-order optimization method, called asynchronous block coordinate descent with time perturbation (ATP), which adopts a time perturbation technique that escapes from saddle points and sub-optimal local points. The details of the proposed method are presented with analyses of convergence and iteration complexity properties. Experiments conducted on real-world machine learning problems validate the efficacy of our proposed method. The experimental results demonstrate that time perturbation enables ATP to escape from saddle points and sub-optimal points, providing a promising way to handle nonconvex optimization problems with inequality constraints employing asynchronous block coordinate descent. The asynchronous parallel implementation on shared memory multi-core platforms indicates that the proposed algorithm, ATP, has strong scalability.

Complex Network Partitioning Using Label Propagation

We present PuLP (partitioning using label propagation), a parallel and memory-efficient graph partitioning method specifically designed to partition low-diameter networks with skewed degree distributions on shared-memory multicore platforms. Graph partitioning is an important problem in scientific computing because it impacts the execution time and energy efficiency of computations on distributed-memory platforms. Partitioning determines the in-memory layout of a graph, which affects locality, intertask load balance, communication time, and overall memory utilization. A novel feature of our PuLP method is that it optimizes for multiple objective metrics simultaneously, while satisfying multiple partitioning constraints. Using our method, we are able to partition a web crawl with billions of edges on a single compute server in under a minute. For a collection of test graphs, we show that PuLP uses up to $7.8\times$ less memory than state-of-the-art partitioners and is $5.0\times$ faster, on average, than a...

High-Performance Passive Macromodeling Algorithms for Parallel Computing Platforms

This paper presents a comprehensive strategy for fast generation of passive macromodels of linear devices and interconnects on parallel computing hardware. Starting from a raw characterization of the structure in terms of frequency-domain tabulated scattering responses, we perform a rational curve fitting and a postprocessing passivity enforcement. Both algorithms are parallelized and cast in a form that is suitable for deployment on shared-memory multicore platforms. Particular emphasis is placed on the passivity characterization step, which is performed using two complementary strategies. The first uses an iterative restarted and deflated rational Arnoldi process to extract the imaginary Hamiltonian eigenvalues associated with the model. The second is based on an accuracy-controlled adaptive sampling. Various parallelization strategies are discussed for both schemes, with particular care on load balancing between different computing threads and memory occupation. The resulting parallel macromodeling flow is demonstrated on a number of medium- and large-scale structures, showing good scalability up to 16 computational cores.

Tiled-MapReduce

The prevalence of chip multiprocessors opens opportunities of running data-parallel applications originally in clusters on a single machine with many cores. MapReduce, a simple and elegant programming model to program large-scale clusters, has recently been shown a promising alternative to harness the multicore platform. The differences such as memory hierarchy and communication patterns between clusters and multicore platforms raise new challenges to design and implement an efficient MapReduce system on multicore. This article argues that it is more efficient for MapReduce to iteratively process small chunks of data in turn than processing a large chunk of data at a time on shared memory multicore platforms. Based on the argument, we extend the general MapReduce programming model with a “tiling strategy”, called Tiled - MapReduce (TMR). TMR partitions a large MapReduce job into a number of small subjobs and iteratively processes one subjob at a time with efficient use of resources; TMR finally merges the results of all subjobs for output. Based on Tiled-MapReduce, we design and implement several optimizing techniques targeting multicore, including the reuse of the input buffer among subjobs, a NUCA/NUMA-aware scheduler, and pipelining a subjob’s reduce phase with the successive subjob’s map phase, to optimize the memory, cache, and CPU resources accordingly. Further, we demonstrate that Tiled-MapReduce supports fine-grained fault tolerance and enables several usage scenarios such as online and incremental computing on multicore machines. Performance evaluation with our prototype system called Ostrich on a 48-core machine shows that Ostrich saves up to 87.6% memory, causes less cache misses, and makes more efficient use of CPU cores, resulting in a speedup ranging from 1.86x to 3.07x over Phoenix. Ostrich also efficiently supports fine-grained fault tolerance, online, and incremental computing with small performance penalty.

Parallel Iterative Solution Schemes for the Analysis of Air Foil Bearings

AbstractIn an air foil bearing analysis the model is usually solved iteratively due in part to the nonlinearity of the modeling Reynolds equation and the compliance of the bearing surface. The solution procedure requires a multiple-level-deep nested iteration, which involves extended solution time and convergence difficulty. In this study, a simple air foil bearing model is used and the compressible-fluid Reynolds equation for modeling gas lubrication is linearized by Newton's method. The discretized equation is solved by one of the two parallel iterative methods, red-black or strip partition successive-over-relaxation (SOR) method. The parallel programming is conducted using OpenMP programming in an eight-core work-station. Then, a numerical damping scheme for the film-profile convergence is presented. Finally, a root-finding process is conducted to iteratively attain the eccentricity of the bearing for a given load. It is found that the numerical damping step is crucial, which allows the use of a larger relaxation factor to have a fast rate of convergence. Both the parallel SOR methods are easy to implement and the red-black SOR method exhibits better efficiency in the studied cases. This study presents a parallel computing scheme for analyzing air foil bearing of bump-type by today's shared-memory multicore platforms.

Communication avoiding successive band reduction

The running time of an algorithm depends on both arithmetic and communication (i.e., data movement) costs, and the relative costs of communication are growing over time. In this work, we present both theoretical and practical results for tridiagonalizing a symmetric band matrix: we present an algorithm that asymptotically reduces communication, and we show that it indeed performs well in practice. The tridiagonalization of a symmetric band matrix is a key kernel in solving the symmetric eigenvalue problem for both full and band matrices. In order to preserve sparsity, tridiagonalization routines use annihilate-and-chase procedures that previously have suffered from poor data locality. We improve data locality by reorganizing the computation, asymptotically reducing communication costs compared to existing algorithms. Our sequential implementation demonstrates that avoiding communication improves runtime even at the expense of extra arithmetic: we observe a 2x speedup over Intel MKL while doing 43% more floating point operations. Our parallel implementation targets shared-memory multicore platforms. It uses pipelined parallelism and a static scheduler while retaining the locality properties of the sequential algorithm. Due to lightweight synchronization and effective data reuse, we see 9.5x scaling over our serial code and up to 6x speedup over the PLASMA library, comparing parallel performance on a ten-core processor.