Shared Hardware Platform Research Articles

A Roadmap for NF-ISAC in 6G: A Comprehensive Overview and Tutorial.

Near-field (NF) integrated sensing and communication (ISAC) has the potential to revolutionize future wireless networks. It enables simultaneous communication and sensing operations on the same radio frequency (RF) resources using a shared hardware platform, maximizing resource utilization. NF-ISAC systems can improve communication and sensing performance compared to traditional far-field (FF) ISAC systems by exploiting the unique propagation characteristics of NF spherical waves with an additional distance dimension. Despite its potential, NF-ISAC research is still in its early stages, and a comprehensive survey of the technology is lacking. This paper systematically explores NF-ISAC technology, providing an in-depth analysis of both NF and FF systems, their applicability in various scenarios, and different channel models. It highlights the advantages and philosophies of ISAC, examining both narrow-band and wide-band NF-ISAC systems. Case studies and simulations offer deeper insights into NF-ISAC design philosophies. Additionally, the paper reviews the existing NF-ISAC literature, methodologies, potentials, and conclusions, and discusses future research areas, challenges, and applications.

An I/O Virtualization Framework With I/O-Related Memory Contention Control for Real-Time Systems

Modern applications are often characterized by a tight interaction with I/O devices. At the same time, many application domains are also facing a shift toward an integrated approach where multiple applications with mixed levels of safety and security need to co-exist on top of a shared hardware platform, which is typically managed by a hypervisor. This gives rise to the need for a predictable mechanism allowing multiple virtual machines to share I/O devices, while at the same time controlling contention delays when they access global memory. To deal with these shortcomings, this article proposes an I/O virtualization framework providing support for controlling the I/O-related memory contention by leveraging the ARM QoS-400 regulators. Extensive experiments are performed to compare the proposed solution with the Xen hypervisor, showing improvements up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8\times $ </tex-math></inline-formula> when controlling the I/O-related memory contention.

Minimizing Stack Memory for Partitioned Mixed-criticality Scheduling on Multiprocessor Platforms

A Mixed-Criticality System (MCS) features the integration of multiple subsystems that are subject to different levels of safety certification on a shared hardware platform. In cost-sensitive application domains such as automotive E/E systems, it is important to reduce application memory footprint, since such a reduction may enable the adoption of a cheaper microprocessor in the family. Preemption Threshold Scheduling (PTS) is a well-known technique for reducing system stack usage. We consider partitioned multiprocessor scheduling, with Preemption Threshold Adaptive Mixed-Criticality (PT-AMC) as the task scheduling algorithm on each processor and address the optimization problem of finding a feasible task-to-processor mapping with minimum total system stack usage on a resource-constrained multi-processor. We present the Extended Maximal Preemption Threshold Assignment Algorithm (EMPTAA), with dual purposes of improving the taskset’s schedulability if it is not already schedulable, and minimizing system stack usage of the schedulable taskset. We present efficient heuristic algorithms for finding sub-optimal yet high-quality solutions, including Maximum Utilization Difference based Partitioning (MUDP) and MUDP with Backtrack Mapping (MUDP-BM), as well as a Branch-and-Bound (BnB) algorithm for finding the optimal solution. Performance evaluation with synthetic task sets demonstrates the effectiveness and efficiency of the proposed algorithms.

Complex event models for automotive embedded systems

The adherent need for computational power in highly automated driving will lead to fewer control units with larger computational power, eventually replacing a large number of a vehicle’s electric control units by so-called vehicle control computers. As a result, high-level functionality will no longer be realized by co-designing software and hardware, but instead by integrating software from different suppliers onto a shared hardware platform. In order to ensure that this functionality will operate according to system specifications, the integrator will need to ensure that requirements related to performance and timing are fulfilled. However, solely relying on e.g. periodical or event triggered activation patterns when integrating third-party software without taking into account external triggering information may lead to overly pessimistic estimations, thus leading to unnecessarily expensive hardware or even preventing feasible configurations. In this work, we provide a comprehensive overview of activation patterns that are employed in the automotive industry and a detailed description of their semantics. We also propose novel event models corresponding to these activation patterns in order to enable the application of performance analysis techniques. We demonstrate the usage of these models on a case study in the context of compositional performance analysis, and quantify the improvement when bounding response times in comparison to the usage of chained task sets. Our experimental results show that the accurate representation of occurrence schemes using specialized event models allows to reduce the pessimism by up to 32.3% compared to using traditional modeling techniques. Finally, we discuss the results along with the impact on the determinism of an application’s temporal behavior.

Clock Synchronization in Virtualized Distributed Real-Time Systems using IEEE 802.1AS and ACRN

Virtualization of distributed real-time systems enables the consolidation of mixed-criticality functions on a shared hardware platform thus easing system integration. Time-triggered communication and computation can act as an enabler of safe hard real-time systems. A time-triggered hypervisor that activates virtual CPUs according to a global schedule can provide the means to allow for a resource efficient implementation of the time-triggered paradigm in virtualized distributed real-time systems. A prerequisite of time-triggered virtualization for hard real-time systems is providing access to a global time base to VMs as well as to the hypervisor. A global time base is the result of clock synchronization with an upper bound on the clock synchronization precision. We present a formalization of the notion of time in virtualized real-time systems. We use this formalization to propose a virtual clock condition that enables us to test the suitability of a virtual clock for the design of virtualized time-triggered real-time systems. We discuss and model how virtualization, in particular resource consolidation versus resource partitioning, degrades clock synchronization precision. Finally, we apply our insights to model the IEEE~802.1AS clock synchronization protocol and derive an upper bound on the clock synchronization precision of IEEE 802.1AS. We present our implementation of a dependent clock for ACRN that can be synchronized to a grandmaster clock. The results of our experiments illustrate that a type-1 hypervisor implementing a dependent clock yields native clock synchronization precision. Furthermore, we show that the upper bound derived from our model holds for a series of experiments featuring native as well as virtualized setups.

Clock Synchronization in Virtualized Distributed Real-Time Systems Using IEEE 802.1AS and ACRN

Virtualization of distributed real-time systems enables the consolidation of mixed-criticality functions on a shared hardware platform, easing system integration. Time-triggered communication and computation can act as an enabler of safe hard real-time systems. A time-triggered hypervisor that activates virtual CPUs according to a global schedule can provide the means to allow for a resource-efficient implementation of the time-triggered paradigm in virtualized distributed real-time systems. A prerequisite of time-triggered virtualization for hard real-time systems is providing access to a global time base to VMs and the hypervisor. A global time base results from clock synchronization with an upper bound on the clock synchronization precision . We present a formalization of the notion of time in virtualized distributed real-time systems. We use this formalization to propose a virtual clock condition that enables us to test the suitability of a virtual clock for the design of virtualized time-triggered real-time systems focusing on clock synchronization. We discuss and model how virtualization, particularly resource consolidation versus resource partitioning, degrades clock synchronization precision. Finally, we apply our insights to model the IEEE 802.1AS clock synchronization protocol and derive an upper bound on the clock synchronization precision of IEEE 802.1AS in a virtualized distributed real-time system. We present our implementation of a dependent clock for ACRN that can be synchronized to a grandmaster clock. The results of our experiments illustrate that a type-1 hypervisor like ACRN implementing the dependent clock paradigm yields native clock synchronization precision. Furthermore, we show that the upper bound of clock synchronization precision derived from our model holds for a series of experiments featuring native and virtualized setups.