Shared Buffer Switch Research Articles

Buffer management for lossless service in shared buffer switches

Fair scheduling and buffer management are two typical approaches to provide differentiated service. Fair scheduling algorithms usually need to keep a separate queue and maintain associated state variables for each incoming flow, which makes them difficult to operate and scale. On the contrary, buffer management (in conjunction with FIFO scheduling) needs only a constant amount of state information and processing, and can be efficiently implemented. In this paper, we consider using buffer management to provide lossless service for guaranteed performance flows in shared buffer switches. We study the buffer size requirement and buffer allocation strategies by starting with the single output switch and then extending the analytical results to the general multiple output switch. We present a universally applicable buffer allocation method for assuring lossless service, and validate the correctness of the theoretical results through simulations.

A shared buffer memory switch with multicast function using generalized two‐level priority control

AbstractIn the future, various multicast applications are anticipated for ATM networks, and many studies have examined ATM switches having the multicast function. In a shared buffer switch, the cell loss performance is clearly improved by unicast priority control that gives send priority to the unicast cell in an address copy switch. However, if the multicast traffic increases, a reduction in the priority control effect becomes a problem. To solve this unicast priority control problem, in this paper, we propose two generalized two‐level priority control schemes (deterministic‐threshold scheme and adaptive‐threshold scheme) that give priority to cells having the number of copies below some threshold. The deterministic‐threshold scheme sets the optimum threshold when the traffic state is known, and clearly reduces the cell loss probability even when the ratio of multicast cells in the input traffic is high. The problem becomes what to set the threshold to because the optimum threshold changes depending on the traffic state in this scheme. The adaptive‐threshold scheme always maintains the priority control effect by automatically changing the threshold in response to traffic variations based on the result obtained from the deterministic‐threshold scheme. We use simulations to compare the adaptive scheme to conventional schemes and demonstrate the effectiveness of the adaptive‐threshold scheme. © 2004 Wiley Periodicals, Inc. Electron Comm Jpn Pt 1, 87(8): 63–70, 2004; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecja.10111

QoS‐oriented traffic management in multimedia satellite systems

AbstractThe next generation of satellite systems will likely use some on‐board switching techniques enabling the direct transmission of data from any up‐link spot‐beam to any down‐link spot‐beam. If the switch used in the payload of the system is an ATM‐based shared buffer switch, some losses and delays can occur. Fortunately, these drawbacks can be fought thanks to some buffer management policies (HSPO, SMXQ, EPD) that either ensure low delay or low loss ratio.Real‐time (voice or MPEG video streams) and non‐real‐time applications (file transfer, email, web browsing using TCP/IP protocols) should be carried over these satellite systems with different quality of service (QoS) requirements. Different combinations of buffer management policies are presented to guaranty the QoS required by the user. Especially, special emphasis is put on the way to transmit efficiently layer 3 messages (IP datagrams) within a mix of traffic in order to avoid some high layer retransmission techniques (provided in TCP for instance) wasting both time and bandwidth. Copyright © 2003 John Wiley & Sons, Ltd.

Queuing analysis of shared‐buffer ATM switches with grouped output channels

AbstractShared buffering and channel grouping are powerful techniques with great benefits in terms of both performance and implementation. Shared‐buffer switches are known to have better performance and better utilization than input or output queued switches. With channel grouping, a cell is routed to a group of channels instead of a specific output channel. In this way, congestion due to output contention can be minimized and the switch performance can therefore be greatly improved. Although each technique is well known by itself in the traditional study of queuing systems, their combined use in ATM networks has not been much explored previously. In this paper, we develop an analytical model for a shared‐buffer ATM switch with grouped output channels. The model is then used to study the switch performance in terms of cell loss probability, cell delay and throughput. In particular, we study the impact of the channel grouping factor on the buffer requirements. Our results show that grouping the output channels in a shared‐buffer ATM switch leads to considerable savings in buffer space. Copyright © 2001 John Wiley & Sons, Ltd.

A new shared-buffer packet switch in ATM networks

To improve overall cell loss rate and fairness problem in shared-buffer switches, a new output-queued shared-buffer switch is proposed in this paper. In the proposed shared-buffer switches, a novel structure of output queues is used to improve the behavior of cell loss rate and resolve the fairness problem. Performance of the proposed output-queued shared-buffer switch is analyzed and compared. According to the analyzed results, the proposed shared-buffer switches show superior performance and overcome the fairness problem. Besides, the proposed buffer architecture is simple to implement in the high-speed packet switches.

Analysis of shared buffer switches under non-uniform traffic pattern and global flow control

Shared buffer switches do not suffer from head of line blocking which is a common problem in simple input buffering. Shared buffer switches have previously been studied under uniform and unbalanced traffic patterns. However, due to the complexity of the model, it was not possible to fully explore the performance of such a switch, in the presence of a single hot spot. In this paper, we develop a new model for an ATM switch constructed from shared buffered switching elements, and operating under a hot spot traffic pattern. Hot spot traffic is one of more realistic traffic in ATM switching. The model is validated by comparison with simulation results. The model is used to study the switch performance in terms of throughput, cell delay, cell loss probability and the optimal buffer utilization. Numerical results show that, in the presence of hot spot traffic, shared buffer switches degrade more significantly than switches with dedicated input and/or output buffers. The model can be used by switch designers to optimize the design and performance of switches.

Accurate modelling of the queueing behaviour of shared buffer ATM switches

A model for the analysis of multistage switches based on shared buffer switching for Asynchronous Transfer Mode (ATM) networks is developed, and the results are compared with the simulation. Switches constructed from shared buffer switches do not suffer from the head of line blocking which is the common problem in simple input buffering. The analysis models the state of the entire switch and extends the model introduced by Turner to global flow control with backpressure mechanism. It is shown that buffer utilization is better and throughput improves significantly compared with the same switch using local flow control policy. Copyright © 1999 John Wiley & Sons, Ltd.

Accurate modelling of the queueing behaviour of shared buffer ATM switches

A model for the analysis of multistage switches based on shared buffer switching for Asynchronous Transfer Mode (ATM) networks is developed, and the results are compared with the simulation. Switches constructed from shared buffer switches do not suffer from the head of line blocking which is the common problem in simple input buffering. The analysis models the state of the entire switch and extends the model introduced by Turner to global flow control with backpressure mechanism. It is shown that buffer utilization is better and throughput improves significantly compared with the same switch using local flow control policy. Copyright © 1999 John Wiley & Sons, Ltd.

An accurate performance model of shared buffer ATM switches under hot spot traffic

Asynchronous transfer mode (ATM) switches based on shared buffering are known to have better performance and buffer utilization than input or output queued switches. Shared buffer switches do not suffer from head of line blocking which is a problem in simple input buffering. Shared buffer switches have previously been studied under uniform and unbalanced traffic patterns. However, due to the complexity of the model, the performance of such a switch, in the presence of a single hot spot, has not been fully explored. In this article, we develop a model for a multistage ATM switch constructed of shared buffer switching elements and operating under a hot spot traffic pattern. The model is used to study the switch performance in terms of the throughput, cell delay, cell loss probability and the optimal buffer size.

Large scale enterprise ATM node with per-VC traffic control

On the backbone nodes of enterprise networks which handle data and voice traffic, complicated Quality of Service (QoS) capability, transmission efficiency, and high reliability are required. ATM technology satisfies those requirements. We have developed a large scale enterprise ATM node based on the shared buffer switch architecture. In the node, per-VC traffic control functions are implemented at low cost using centralized control of buffer write and read. In this paper, we explain the detail of the per-VC traffic control functions and show the performance results of ABR control using the node.

Queuing analysis of shared-buffer switches with control scheme under bursty traffic

Shared-buffer switches have many advantages such as relatively low cell loss rate and good buffer utilization, and they are increasingly favoured in recent VLSI switch designs for ATM. However, their performance degrades dramatically under nonuniform traffic due to the monopolization of the buffer by some favoured cells. To overcome this, restricted types of sharing and hot-spot pushout (HSPO) have been proposed, and the latter has been shown by simulation to perform better in all situations. In this paper we develop an analytical model for performance evaluation of a shared-buffer asynchronous transfer mode (ATM) switch with HSPO under bursty traffic. This analytical model is an improved version of the first model ever developed for this purpose. We balance the relative queues to approximate the effects of pushout, while keeping only four state-variables, and our model gives a good agreement with simulation, for calculating throughput and cell loss.

Video-server designs for supporting very large numbers of concurrent users

We present a design for a video server in which video content is stored in special video-delivery subsystems attached directly to network components such as switches or high-speed-network ports rather than the magnetic disk storage attached to conventional computer systems. Video is preformatted and stored in the form of network packets. This design approach overcomes the CPU- and I/O-bandwidth limitations of conventional computers in executing the file-system and network-protocol code for many concurrent video streams, resulting in higher performance at a lower cost. Two designs for the approach are discussed. The first extends the packet buffer of a shared-buffer switch with additional memory for storing the video packets. The second design uses a stream controller as the interface between an array of disks and a traditional switch or network port. We have built a prototype based on the second design. To avoid interference on the disks, data is interleaved across all disks connected to a stream controller in units of fixed playback time. This also reduces the jitter in the response time of the disks and, therefore, the size of the buffers needed to maintain interruption-free delivery. The cost benefits of both approaches are discussed.

Physical performance limits for shared buffer ATM switches

Performance studies, linking ATM switch capabilities to physical limitations imposed by integrated circuit technology, have been scarce. This paper explores trends in circuit capabilities, and makes projections toward the 0.25-/spl mu/m technologies that will be available to all switch designers in the year 2000. The limits imposed by circuit technology are applied to shared buffer ATM switches. We determine requirements and physical limits for buffer capacity, buffer throughput, chip I/O throughput, and power dissipation. As a result, we are able to project chip counts, aggregate switch throughputs, and switch dimensions. As well, performance capabilities of single-chip shared buffer switches are estimated. A single-chip shared buffer switch implemented in 0.25-/spl mu/m technology will be capable of an aggregate throughput of 1.3 Tb/s, will accomplish almost arbitrarily low cell loss rates for bursty traffic, and may be integrated together with translation tables supporting hundreds of connections per port.

Buffer occupancy in ATM switches with single hot spot

ATM switches based on shared buffering are known to have better buffer utilisation. However, in the presence of hot spot traffic, buffers become monopolised in favour of hot output. In the Letter, we present the effect of buffer monopoly in a shared buffer switch and discuss the solutions to this phenomenon.

A flexible shared-buffer switch for ATM at [formula omitted] rates

This paper presents the architecture of a very high-speed VLSI packet switch and its performance. The switch, called PRIZMA, is suited for broadband telecommunications, based on ATM, the Asynchronous Transfer Mode. However, the concept is not restricted to ATM-oriented architectural environments. There may be applications within private networks, independent of whether they are ATM-based. There may also be other potential applications such as multiprocessor interconnection. The architecture of the PRIZMA switch follows the architecture of its lower-speed earlier version (H. Ahmadi et al., Int. J. Digital Analog Cabled Syst. 2 (4) (1989) 277–287) to a large degree: It is based on a single-chip switch element that exploits the performance advantage of output queuing and from which larger, self-routing single-stage or multistage switch fabrics can be constructed in a modular way. However, compared to the precursor, higher performance is achieved by output queues that now are configured as a dynamically shared memory. This shared memory can also be expanded by linking multiple switch elements. Owing to novel parallel structures inside the switch element, VLSI implementation is possible for transmission rates on the order of a gigabit per second per port. In the last section of this paper, performance results are presented for a switch in a single-stage configuration as well as for the case of a three-stage switch fabric.

Dimensioning of an ATM switch with shared buffer and threshold priority

A number of recent studies have addressed the use of priority mechanisms in Asynchronous Transfer Mode (ATM) switches. This investigation concerns the performance evaluation and dimensioning of a shared-buffer switching element with a threshold priority mechanism (partial buffer sharing). It assumes that incoming ATM ceils are distinguished by a space priority assignment, i.e., loss of a high priority cell should be less likely than loss of a low priority cell. The evaluation method is analytic, based on an approximate discrete-time, finite-state Markov model of a switch and its incoming traffic. The development focuses on the formulation of steady-state loss probabilities for each priority class. Evaluation of delay measures for each class is also supported by the model; results concerning the latter are illustrated without development. The analysis of loss probabilities is then used to dimension the buffer capacity and threshold level such that required maximum cell loss probabilities are just satisfied for each cell type. Moreover, when so dimensioned with respect to relatively stringent loss requirements, i.e., probabilities of 10 10 and 10 s for high and low priority cells, respectively, we find that both loss performance and resource utilization are appreciably improved over a comparable switch without such a mechanism.

Improved queueing analysis of shared buffer switching networks

The authors describe several methods for analyzing the queueing behavior of switching networks with flow control and shared buffer switches. They compare the various methods on the basis of accuracy and computation speed, where the performance metric of most concern is the maximum throughput. The best of the methods accurately predicts throughput for multistage networks constructed from large switches (>or=8 ports).< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A one-chip scalable 8*8 ATM switch LSI employing shared buffer architecture

The authors present a one-chip scalable 8*8 shared buffer switch LSI which includes a 256-cell buffer. Speedup, flow control, and input slot rotation functions are provided in order to interconnect LSIs for scaling-up without degrading cell loss rates. Computer simulations show that these functions bring a satisfactory result and can make the cell loss- rate for a Clos three-stage network superior to that for the output buffer switch which includes the same amount of buffer space. A 0.8 mu m BiCMOS process is employed for this LSI. The total number of transistors is one million. This LSI has already been fabricated.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Simulation methods for studying nonstationary behavior of computer networks

Methods for the simulation of the nonstationary behavior of computer networks are discussed. Steady-state performance measures, typically computed over time histories, are modified to be applicable to the nonstationary case by redefining the measures as ensemble statistics. The application of well-known ensemble simulation techniques to determining the modified performance metrics from finite ensembles generated by independent replications is given. The simulation methods are illustrated with a comprehensive tutorial example and with a performance study which gives results for a shared buffer switch.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>