Shallow Trench Structure Research Articles

Monolithic integration of a InP AWG and InGaAs photodiodes on InP platform

We demonstrate a monolithic integration of a photodiode array and a 13 channels arrayed waveguide grating (AWG) grown on InP substrate with a shallow trench structure between the AWG top cladding layer and the photodiode p-doped layer. A smooth epitaxial structure interface is obtained by nonselective regrowth to make the two epitaxial structure compatible and fabrication easy. Three-dimensional finite-difference time-domain(FDTD) solutions are used in the optical simulations. The highest simulation quantum efficiency can achieve 82%. The fabricated PD with a trench structure presents a responsivity of 0.68A/W. The integrated device can achieve a total capacity of more than 200Gb/s.

초고집적용 새로운 회자 구조의 얕은 트랜치 격리의 특성 분석

본 논문에서는, 초고집적 CMOS를 위한 얕은 트랜치 격리로 기존의 수직 구조에서 내부 임계전압과 활성 영역의 스트레스 영향을 개선시키고자 한다. 이를 위해서 제안한 구조는 회자 모양의 얕은 트랜치 격리 구조이며, 기존 수직 구조와 제안한 구조에 대해서 전자농도 분포와 게이트 바이어스 대 에너지 밴드 형태, 열전자 스트레스와 열 손상의 유전 강화 전계를 분석 하고자 한다. 물리적 기본 모델들은 TCAD 툴을 이용하며, 집적화 소자들에 있어서 분석 조건은 주위 조건과 스트레스 인가이다. 분석 결과, 얕은 트랜치 격리 구조가 소자의 크기가 감소됨에 따라서 수동적인 전기적 기능이며, 트랜지스터 응용에서 제안한 회자 구조의 얕은 트랜치 격리 구조가 전기적 특성에서 전위차 전계와 포화 임계 전압이 높게 나타났으며, 활성영역에서 스트레스의 영향은 감소되었다. 이 결과 데이터를 바탕으로 제작한 소자의 결과 분석도 시뮬레이션 결과 데이터와 거의 동일하였다. In this paper, the conventional vertical structure for VLSI circuits CMOS intend to improve the stress effects of active region and built-in threshold voltage. For these improvement, the proposed structure is shallow trench isolation of moat shape. We want to analysis the electron concentration distribution, gate bias vs energy band, thermal stress and dielectric enhanced field of thermal damage between vertical structure and proposed moat shape. Physically based models are the ambient and stress bias conditions of TCAD tool. As an analysis results, shallow trench structure were intended to be electric functions of passive as device dimensions shrink, the electrical characteristics influence of proposed STI structures on the transistor applications become stronger the potential difference electric field and saturation threshold voltage, are decreased the stress effects of active region. The fabricated device of based on analysis results data were the almost same characteristics of simulation results data.

고집적을 위한 얕은 트랜치 격리에서 제안한 구조의 특성 모의 분석

ABSTRACTIn this paper, We are going to propose the novel structure with improved behavior than the conventional vertical structure for VLSI CMOS circuits. For this, the proposed structure is the moat shape for STI. We want to analysis the characteristics of simulations about the electron concentration distribution, oxide layer shape of hot electron stress, potential flux and electric field flux, electric field fo themal damage and current-voltage characteristics in devices. Physically based models are the ambient and stress bias conditions of TCAD tool. As a analysis results, shallow trench structure were trended to be electric functions of passive as device dimensions shrink. The electrical characteristics influence of proposed STI structures on the transistor applications become stronger the potential difference electric field and saturation threshold voltage, are decreased the stress effects of active region. The fabricated device of based on analysis results data were the almost same characteristics of simulation results data.

TCAD 툴을 이용한 제안된 얕은 트랜치 격리의 시뮬레이션

In this paper, the proposed shallow trench isolation structures for high threshold voltage for very large scale and ultra high voltage integrated circuits MOSFET were simulated. Physically based models of hot-carrier stress and dielectric enhanced field of thermal damage have been incorporated into a TCAD tool with the aim of investigating the electrical degradation in integrated devices over an extended range of stress biases and ambient temperatures. As a simulation results, shallow trench structure were intended to be electric functions of passive, as device dimensions shrink, the electrical characteristics influence of proposed STI structures on the transistor applications become stronger the potential difference electric field and saturation threshold voltage.

제안된 얕은 트랜치 격리에서 구조형태에 따른 제작 및 특성의 시뮬레이션

In this paper, the edge effects of proposed structure in active region for high voltage in shallow trench isolation for very large integrated MOSFET were simulated. Shallow trench isolation (STI) is a key process component in CMOS technologies because it provides electrical isolation between transistors and transistors. As a simulation results, shallow trench structure were intended to be electric functions of passive, as device dimensions shrink, the electrical characteristics influence of proposed STI structures on the transistor applications become stronger the potential difference electric field and saturation threshold voltage.

Raman Investigation of Stress for Shallow Trench

A trench is used as a storage capacitor in dynamic memory (DRAM) technologies (deep storage trenches), or as an isolation structure in CMOS, bipolar and BiCMOS technologies. But a shallow trench structure has also been shown to be a major factor in substrate defect generation during processing. Such defect generation is directly related to mechanical stresses existing around the trench. This stress can be monitored, using Raman spectroscopy, to a stress resolution of 10MPa and a spatial resolution of 0.2μm. In this paper, a trench structure is designed and fabricated, and the test results for local stresses within the trench are shown to be in good correspondence with theory.

Microwave PIN diodes for GaAs IC

The letter describes the design and fabrication techniques for successful realisation of two types of GaAs PIN diodes which lend themselves to integration into GaAs ICs. PIN diodes with a new shallow trench structure exhibit superior microwave performance to the interdigitated structure.