SGOI Substrates Research Articles

(Invited) SiGe/SOI System: Mechanisms of Condensation and Strain Relaxation

Silicon-Germanium strain engineering has been used for more than two decades in silicon based devices and has contributed to the scaling down of a transistor’s size and to significant improvements in device performance. However, while conventional silicon-germanium based electronics has experienced rapid and steady growth, thanks to this continuous miniaturization of transistors, this trend cannot continue indefinitely. Industry has already moved to alternate methods such as FinFET devices, in which a thin silicon channel is placed vertically, and the FD-SOI (FD-SGOI) design consisting of a thin film Si(SiGe) channel placed horizontally. For nodes scaled down below 28 nm, low power operation will be inherently hindered by both the imperfect interface, non-uniformity of ultra-thin films and quantum confinement effects, which increase the effective bandgap. In these devices, despite the intense research activity on the strained SiGe ultra-thin body, which accounts for a large portion of such microelectronic devices (below the 45 nm node), we still fail to properly understand the mechanisms that limit hole and electron mobilities in SGOI layers. In addition, one of the main challenges for Si based devices remains the fabrication of efficient group-IV photon sources / photon detectors compatible with the microelectronic industry, which would usefully replace the integration of III-V heterostructures on Si. The major bottleneck is that group-IV semiconductor elements have indirect bandgaps, but with possibilities of being transformed to direct bandgaps using strain engineering strategies.In this presentation, we will review the formation mechanism of Ge-rich layers on SOI by condensation at different temperatures. TEM cross-section and GPA analysis of the heterostructures will be presented. We will also report the physical and optical properties of these heterostructures. Special attention is devoted to the influence of the SiGe thickness reduction (up to few MLs), where quantum confinement is prominent in the optical properties of the layers. Raman and PL results will be presented to better explain such confinement behavior. We show that novel SGOI substrates could represent a key strategy for the fabrication of future photonic devices.

(Invited) New Strategies to Produce Light Emitters with Si-based Nanostructures

Silicon-Germanium strain engineering has been used for more than two decades in silicon based devices and has contributed to the scaling down of a transistor’s size and to significant improvements in device performance. However, while conventional silicon-germanium based electronics has experienced rapid and steady growth, thanks to this continuous miniaturization of transistors, this trend cannot continue indefinitely. Industry has already moved to alternate methods such as FinFET devices, in which a thin silicon channel is placed vertically, and the FD-SOI (FD-SGOI) design consisting of a thin film Si(SiGe) channel placed horizontally. For nodes scaled down below 28 nm, low power operation will be inherently hindered by both the imperfect interface, non-uniformity of ultra-thin films and quantum confinement effects, which increase the effective bandgap. In these devices, despite the intense research activity on the strained SiGe ultra-thin body, which accounts for a large portion of such microelectronic devices (below the 45 nm node), we still fail to properly understand the mechanisms that limit hole and electron mobilities in SGOI layers. In addition, one of the main challenges for Si based devices remains the fabrication of efficient group-IV photon sources / photon detectors compatible with the microelectronic industry, which would usefully replace the integration of III-V heterostructures on Si. The major bottleneck is that group-IV semiconductor elements have indirect bandgaps, but with possibilities of being transformed to direct bandgaps using strain engineering strategies.In this presentation, we will review the formation mechanism of Ge-rich layers on SOI by condensation at different temperatures. TEM cross-section and GPA analysis of the heterostructures will be presented. We will also report the physical and optical properties of these heterostructures. Special attention is devoted to the influence of the SiGe thickness reduction (up to few MLs), where quantum confinement is prominent in the optical properties of the layers. Raman and PL results will be presented to better explain such confinement behavior. We show that novel SGOI substrates could represent a key strategy for the fabrication of future photonic devices.

(Invited) Strained-SiGe Channel FinFETs for High-Performance CMOS: Opportunities and Challenges

The effectiveness of widely-used CMOS stressors, such as compressive stress liners and embedded source/drain is significantly decreased in the state-of-the-art CMOS as the gate pitch is scaled down and device architecture is transformed from planar to 3D non-planar architectures, such as FinFETs. The issue is more pronounced for FinFETs fabricated on the SOI substrates. It is well known that SiGe is a great candidate for p-type MOSFETs due to its intrinsic lower effective mass and better transport properties than Si and has been utilized in CMOS industry for IBM SOI 32nm and 22nm generations, as a key knob to adjust the PFET threshold voltage and performance enhancement [1, 2]. However, it is shown that SiGe with moderate Ge content and no strain does not provide noticeable transport (neither long-channel nor short-channel) benefit over Si and it is believed that the strain plays a significant role in high-performance (HP) SiGe channel pFETs [3]. The strain state in typical thin SiGe substrates grown on bulk Si or SOI is biaxial compression. It has been shown that by patterning of biaxially strained SiGe layers, strain can be transformed to asymmetric strain (uniaxial for FinFET) where the effective mass is significantly lowered and higher hole velocities can be achieved. Hole transport can be significantly improved by increasing the Ge content as well as the built-in strain, while the second component (strain) has a stronger impact on the transport enhancement. However, higher-Ge content SiGe offers reduced bandgap and may result in increased gate-induced –drain-leakage (GIDL) and high off current due to increased band-to-band or trap-assisted tunneling. This brings concern for some CMOS applications, such as I/O devices and SRAM. Moreover, the interface passivation for higher Ge content SiGe is extremely challenging and can cause significant sub-threshold leakage and degraded low field mobility. The direct consequence is the degraded short-channel on-state current at the target off-current at a scaled power-supply voltage, VDD. In order to experimentally investigate the device characteristics of SiGe FinFETs, we have fabricated strained-Si1-xGex-on-insulator pMOS FinFETs with Ge fraction, x~0.3-0.5 using CMOS-compatible process flows which allow us co-integration with Si or strained-Si for n-type transistors. Highly-compressively-strained SGOI substrates were fabricated using Ge condensation processes and strain transformation to uniaxial was verified by Raman spectroscopy. A gate-first high-K/metal-gate flow with ion-implant-free raised-S/D and aggressively scaled fin and spacer dimensions has been developed to fabricate devices with aggressively scaled gate lengths [4]. A Si-cap-free scheme was developed for the interface passivation to allow CET scaling and eliminate the epitaxial related issues on the 3D architectures. We have observed that non-optimized passivation may result in relatively high interface trap densities and sub-threshold slopes (SS) around 75-80mV/dec for x~0.3 and over 80mV/dec for x~0.5. However, by optimizing the passivation process using a Si-cap-free approach, impressive SS=65mV/dec and 68mV/dec has been achieved for SGOI FinFETs with x~0.3 and x~0.5, respectively. Moreover, significant transport benefit in terms of mobility and drive current has been achieved due to the improved passivation [5]. As a result, we have reported superior mobility characteristic for SGOI pMOS FinFETs with x~0.5 over the state of the art Si, SiGe or relaxed-Ge FinFETs [6]. We have also investigated the short-channel GIDL characteristics of surface-channel strained-Si1-xGex pMOS FinFETs. We have shown devices having a minimum GIDL current of 1nA/μm for x~0.3 and 20nA/μm for x~0.5 at an operating voltage of VDD=0.8V and an operating temperature of 50°C. Temperature-dependent leakage current measurements demonstrate that the GIDL caused by band-to-band tunneling is the dominant leakage mechanism as compared to trap-assisted tunneling for both cases [7]. In summary, we have reported process integration and electrical characterization of SGOI FinFETs with aggressively scaled gate and fin dimensions and Ge content x~0.3-0.5 using an improved Si-cap-free surface passivation process. SiGe-OI FinFETs with x~0.3 can offer superior pMOS characteristics and are promising candidate for both high-performance and low-power applications. On the other hand, while SiGe-OI FinFETs with x~0.5 can offer extremely high mobility and high current drive and transconductance which is applicable to high-performance CMOS, their operation even at low VDD could be a concern for low-power applications, similar to the state-of-the-art Ge FinFETs [8]. S. Krishnan et al., IEEE IEDM, 634 (2011).C. Ortolland et al., IEEE IEDM, 236 (2013).A. Khakifirooz et al., IEEE EDL, 34, 1358 (2013).P. Hashemi et al., Symp. VLSI Tech., 18 (2013).P. Hashemi et al., Symp. VLSI Tech., 18 (2014).P. Hashemi et al., IEEE IEDM, 16.1 (2014).K. Balakrishnan et al., IEEE DRC, 183 (2014).B. Duriez et al., IEEE IEDM, 522 (2013).

(Invited) Strained SiGe on Insulator FinFETs: a P-FET Candidate for 10nm Node

Performance enhancement using conventional stress elements such as stress liners or embedded source/drain is significantly decreased at extremely tight gate pitch, required for 10nm node and beyond [1]. This issue is more pronounced for non-planar architectures such as FinFETs, especially those made on SOI substrates. For p-type MOSFETs, SiGe is a great candidate due to its intrinsic lower effective mass and better transport properties than Si. SiGe has been utilized in CMOS industry for IBM SOI 32nm and 22nm generations, as a knob to adjust the PFET threshold voltage and performance enhancement [2, 3]. However, it is shown that SiGe with moderate Ge content and no strain does not provide noticeable short-channel benefit over Si and as a result, strain plays a significant role in high-performance SiGe channel pFETs [4]. While higher Ge content SiGe materials can offer lower effective mass and have potential for better transport properties [5], their reduced bandgap by increasing Ge content brings concern for some CMOS applications. This results in increased gate-induced drain leakage and high off current due to increased band-to-band or trap-assisted tunneling [6]. Moreover, the interface passivation for higher Ge content SiGe is extremely challenging resulting in significant sub-threshold leakage and degraded low field mobility. The direct consequence is the degraded short channel on-state current at the target off-current at a scaled VDD. It has been shown that by patterning of biaxially strained SiGe layers, strain can be transformed to asymmetric strain [7, 8] where the effective mass is significantly lowered and higher hole velocities can be achieved [5]. Therefore, the strain state in a scaled fin fabricated from biaxially strained substrates is pure uniaxial with optimal benefit for hole transport. The combination of uniaxial strain with great electrostatic integrity due to the non-planar device architecture as well as more manufacturing-friendly process, makes the moderate Ge content (such x=0.2-0.3) SiGe a very promising candidate for future generation of FinFETs. In order to evaluate the performance of s-SiGe FinFETs, SGOI substrates were fabricated using Ge condensation technique. This process is SOI CMOS compatible, where SiGe can be locally condensed in the pFET region while Si can be used for nFET or other on-chip applications. A final Ge fraction of x = 27.5% was measured by XRD, with minimal strain relaxation consistent with SIMS results (Figure 1(a)). The defectivity of SGOI substrates was measured using ex-situ Si capping followed by SECCO etch and dislocation density of ~ 1e4 cm-2 was measured for an optimized epitaxy and Ge condensation process. A gate first process flow was developed to fabricate our SiGe pMOS FinFETs [9]. As s-SiGe reactive-ion-etch resistance is much less than that of Si, the spacer RIE process was optimized to minimize fin recess in S/D regions and thus minimize stress relaxation. Raised S/D regions were formed using an ion-implant-free process by in-situ Boron-doped (ISBD) Si1-yGey (y > 40%) epitaxy with high Boron concentration, and dopant drive-in under the spacer to form the extensions. SGOI fins with vertical sidewalls and widths as scaled as 10nm demonstrated. Figure 1(b) shows typical XTEM of s-SiGe PMOS FinFET with sub-20nm physical gate length.Typical transfer and output characteristics of single-fin SiGe-channel PFETs (Fig. 2) exhibit excellent electrostatics with DIBL~50mV/V and SS ~90 mV/decade. In spite of high REXT ~ 0.4kΩ.μm, ION = 1.1 mA/µm was obtained at IOFF = 100 nA/µm and VDD = 1V. This high on current is attributed to the high source injection velocity exceeding 1e7 cm/s which is higher than SOI FinFETs with no stressors [10], and also higher than state-of the art bulk FinFETs [11]. Moreover, the SiGe PMOS FinFETs offers low off-state leakage suitable for high-performance and low-power applications. These criteria are hard to meet using state of the art Ge pFETs due to the significantly smaller bandgap [12]. In addition, unlike state of the art Ge pFETs, using a metal gate with a mid-gap work-function, target Vth has been achieved. In conclusion, we have demonstrated that s-SiGe channel FinFETs are a promising pFET candidate for future generations of high-performance devices and have a more manufacturable friendly process, than high-Ge content SiGe or Ge.REFERENCES[1] W. Haensch, IBM J. Res. & Dev., 2006. [2] S. Krishnan, IEDM 2011. [3] C. Ortolland, IEDM 2013. [4] A. Khakifirooz, IEEE TED 2009. [5] L. Gomez, IEEE TED, 2009. [6] C. Ni Chleirigh, IEEE TED, 2008. [7] T. Irisawa, IEDM 2005. [8] P. Hashemi, APL 2007. [9] P. Hashemi, VLSI 2013. [10] T. Yamashita, VLSI 2011. [11] C. Auth, VLSI 2012. [12] B. Duriez, IEDM 2013.

A comparative study of self-heating effect of nMOSFETs fabricated on SGOI and SGSOAN substrates

In this work, for the first time, the electrical and thermal characteristics of strained Si/SiGe nanoscale n type metal–oxide–silicon field-effect transistors (MOSFETs) with silicon-on-aluminum nitride (SOAN) substrate are investigated by ISE TCAD. This novel structure is named as SGSOAN nMOSFET. A comparative study of self-heating effect (SHE) of nMOSFETs fabricated on SGOI and SGSOAN are presented in this paper. Numerical study results show that this novel SGSOAN structure can greatly eliminate excessive self-heating in devices, which gives a more promising application for SGOI to work at high temperature.

Comprehensive Study of the Fabrication of SGOI Substrates by the Ge Condensation Technique: Oxidation Kinetics and Relaxation Mechanism

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Effect of NH3 and N2 annealing on the interfacial and electrical characteristics of La2O3 films grown on fully depleted SiGe-on-insulator substrates

The interfacial structure and the electrical properties of pulsed laser deposition derived La2O3 ultra-thin films on fully depleted SiGe-on-insulator (FD SGOI) substrates before and after post-annealing in NH3 and N2, respectively, have been investigated comparatively. The results from high-resolution transmission electron microscopy and x-ray photoelectron spectroscopic revealed that interface reactions take place after the NH3 and N2 annealing process, but, as compared with the N2 annealing process, the NH3 annealing process can effectively decrease the thickness of the interfacial layer and incorporate more nitrogen at the dielectric/SiGe interface, resulting in smaller equivalent oxide thickness. The La2O3 capacitors annealed in NH3 show good capacitance–voltage characteristics with negligible hysteresis, smaller interface trap density and lower gate-leakage current density in comparison with those of capacitors annealed in N2. It is demonstrated that the NH3 annealing process can be a promising technology in improving the quality of high-k dielectric on FD SGOI substrates.

High Hole Mobility SGOI Substrates Obtained by the Germanium Condensation Technique

Thin SGOI substrates with Ge content from 42 to 93% have been produced by the Ge condensation technique and full structural characterization has been carried out. In a second step, the electrical properties of these substrates have been analyzed by the pseudo-MOSFETs technique which allowed the determination of the carrier low field mobilities as well as the density of fixed charges in the buried oxide (BOX) and the density of interface traps at the BOX-SiGe film interface. Optimization of intermediate anneals in argon during the condensation process has made the production of high crystalline quality and high mobility substrates possible (up to 400 cm2/Vs for a 93% SGOI). Opposite trends were observed for holes and electrons: while the hole mobility is increasing with increasing Ge content, the electron mobility decreases. Moreover, the density of interface traps and the density of oxide charges were found to increase with increasing Ge content.

High Hole Mobility SGOI Substrates Obtained by the Germanium Condensation Technique

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High Ge content SGOI substrates obtained by the Ge condensation technique: A template for growth of strained epitaxial Ge

In the first part of this work, the fabrication of silicon germanium-on-insulator substrates (SGOI) by the Ge condensation technique was studied. Ge atomic fractions as high as 93% have been obtained while maintaining nice structural properties of the films. We show that these layers exhibit a large compressive strain and that the strain can be lowered by introducing some annealing steps in argon ambient during the condensation. SGOI substrates with a Ge atomic fraction of 75% were subsequently used as template for the growth of strained epitaxial Ge layers. Because of the important strain in the SGOI, the temperature for the in-situ bake prior to the growth has to be carefully selected in order to avoid relaxation. Ge layers with compressive strain up to −1% and thicknesses up to 40 nm have been obtained. The crystal quality, roughness and thermal stability of the strained Ge layers were finally evaluated.

Epitaxial Regrowth of Ge on SGOI and GeOI Substrates Obtained by Ge Condensation

In this paper, we have investigated the influence of process parameters (bake temperature, bake duration and growth temperature) on the morphology of GeOI substrate thickened by Ge epitaxial regrowth. We have seen that the optimum bake temperature in terms of layer roughness and interfacial contamination is 600{degree sign}C. For higher bake temperatures, the layer morphology is 3D due to a layer dewetting. The efficiency of the surface preparation prior to the epitaxial regrowth has been assessed by Angle resolved X-Ray Photoelectrons Spectroscopy. No residual oxygen contamination has been detected. Furthermore, we have investigated the influence of the growth temperature on the layer morphology and resistivity. For temperatures higher than 450{degree sign}C, some thermal grooving assisted by the crystal defects (cross hatch) occurred and 3D Ge layers were obtained. Finally, GeOI substrates thickened with the best growth condition were evaluated by Pseudo MOSFET technique. An exceptional high hole mobility, beyond 400 cm2/V.s was observed.

Epitaxial Regrowth of Ge on SGOI and GeOI Substrates Obtained by Ge Condensation

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Ge Condensation Technologies for Advanced MOSFETs on SGOI and GOI Substrates

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Study of the Surface Cleaning of GOI and SGOI Substrates for Ge Epitaxial Growth

not Available.

Fabrication and Electrical Characterization of Strained Si-on-insulator/Strained SiGe-on-insulator Dual Channel CMOS structures with High-Mobility Channels

Mobility enhancement technologies by incorporating strain in MOSFETs have been recognized as key technologies for scaled CMOS devices. The most promising channel materials for n- and p-channel MOSFETs are tensily-strained Si and compressively-strained Ge (SiGe), respectively, from the viewpoint of their high mobility values. In this paper, dual channel CMOS structures with strained Si-on-insulator (strained-SOI)-nMOSFETs and strained SiGe-on-insulator (strained-SGOI)-pMOSFETs are demonstrated as well as their high channel mobility and current drive enhancements. Strained Si channels on a relaxed SGOI substrate and Ge-rich strained SGOI channels are located on the nMOS and pMOS regions of the same wafer, respectively. The dual channel structure was fabricated by a CMOS process combined with the Ge condensation process, in which the epitaxially grown SiGe layer on the SOI substrate was locally oxidized at high temperatures. As a result, significant electron- and hole-mobility enhancements for the strained SOI and SGOI channels were observed as well as the drain current enhancements. Based on the measured mobility for the nMOS and pMOS channels in the CMOS devices, CMOS performance enhancement of 30% was estimated.

Engineering strained silicon on insulator wafers with the Smart Cut TM technology

Strained silicon on insulator wafers are today envisioned as a natural and powerful enhancement to standard SOI wafers and/or bulk-like strained Si layers. This paper is intended to demonstrate through miscellaneous structural results how a layer transfer technique such as the Smart Cut TM technology can be used to obtain good quality tensile-strained silicon on insulator wafers. Such a technique uses preferentially hydrogen implantation to peel-off the very top part of an epitaxial stack and transfer it onto another silicon substrate. The formation of an insulator, prior to the bonding onto a new silicon substrate enables the formation of a “semiconductor on insulator” structure. Two approaches based on the Smart Cut technique are considered in this paper. The first one relies on the formation by layer transfer of a relaxed SiGe on insulator (“SGOI”) substrate on which a tensile-strained Si layer is then grown. The second one is based on the transfer of a SiGe relaxed buffer/Si cap stack. A SiGe-free tensile-silicon on insulator (sSOI) substrate is then obtained after the selective etching of the top SiGe layer. The epitaxial layers studied in this article are of two kinds: (i) the thick, nearly fully relaxed SiGe layers (with or without tensile-strained Si layers on top depending on the final structure targeted: SGOI or sSOI) used as the donor wafers in layer transfer operations, and (ii) the thin, relaxed SiGe layers and the thin, tensile-strained Si epitaxial films grown on SGOI substrates. In-depth physical characterizations of these epitaxial layers are used to evaluate the quality of the transferred layers in terms of thickness uniformity, Ge content, strain control, dislocation densities etc… Detailed experiments are also used to demonstrate that these final substrates are compatible with future CMOS applications. The sSOI approach is particularly challenging in this respect as the strain needs to be maintained during many technological operations such as layer transfer, selective removal of the SiGe, high temperature thermal treatments etc. First results showing how the strain is changing during such operations are presented.

Fully Depleted Strained-SOI n- and p-MOSFETs on Bonded SGOI Substrates and Study of the SiGe/BOX Interface

Fully depleted strained-Si n- and p-MOSFETs have been demonstrated on bonded-SiGe-on-insulator (SGOI) substrates. The fully depleted devices show significant electron and hole mobility enhancements of 60 and 35%, respectively, demonstrating that high material quality, thin SGOI substrates can be fabricated by a wafer bonding approach. The bottom SiGe/buried-oxide interface in the SGOI structure and its impact on fully depleted device performance are also investigated.

Fabrication of a strained is on sub-10-nm-thick SiGe-on-insulator virtual substrate

A novel fabrication method for ultra-thin Si 1− x Ge x -on-insulator (SGOI) virtual substrates is proposed for the application of strained silicon-on-insulator (SOI) MOSFETs. Evaluation of the strain in a strained Si layer on this SGOI substrate is also presented. A 9-nm-thick SGOI layer with x=0.56 was formed by dry oxidation of epitaxially grown Si 0.9Ge 0.1 on a SOI substrate. During the oxidation, Ge atoms were rejected from the surface oxide layer and condensed in the remaining SGOI layer without introducing considerable threading dislocations. After removing the surface oxide layer, a 10-nm-thick Si layer was grown on the SGOI layer. TEM and Raman measurements indicated that the Si layer was pseudomorphically grown on the SGOI layer with 1.0% of tensile strain, corresponding to the strain in a Si layer on fully relaxed Si 0.76Ge 0.24. This fabrication method is applicable to fully depleted strained SOI MOSFETs with gate lengths of less than 100 nm, which require relaxed and thin SGOI layers (<10 nm) with high x value ( x>0.3).

Relaxed Silicon-Germanium on Insulator (SGOI)

AbstractWe have fabricated high quality SGOI substrates and demonstrated high mobility enhancement in strained-Si MOSFET's fabricated on the relaxed SGOI substrates with a Ge content of 25%. The substrates were fabricated by wafer bonding. The initial relaxed Si1−xGex layers were grown on Si donor substrates by a graded epitaxial growth technology using ultrahigh vacuum chemical vapor deposition (UHVCVD). The SiGe wafers were then bonded to oxidized silicon handle wafers. Two different approaches have been developed to fabricate SGOI substrates: an etch-back process utilizing a 20% Ge layer as a natural etch stop, and a hydrogen-induced wafer delamination process using H+ implantion. The resultant SiGe film quality was compared among the different approaches. Large-area strained-Si MOSFET's were then fabricated on the SGOI substrates. Epitaxial regrowth was used to produce the upper portion of the relaxed SiGe and the surface strained Si layer. The measured electron mobility shows significant enhancement over both the universal mobility and that of co-processed bulk-Si MOSFET's. This SGOI process has a low thermal budget and thus is compatible with a wide range of Ge contents in Si1−xGex layer.