Series-parallel Reduction Research Articles

Quantum isomorphism of graphs from association schemes

We show that any two Hadamard graphs on the same number of vertices are quantum isomorphic. This follows from a more general recipe for showing quantum isomorphism of graphs arising from certain association schemes. The main result is built from three tools. A remarkable recent result [20] of Mančinska and Roberson shows that graphs G and H are quantum isomorphic if and only if, for any planar graph F, the number of graph homomorphisms from F to G is equal to the number of graph homomorphisms from F to H. A generalization of partition functions called “scaffolds” [23] affords some basic reduction rules such as series-parallel reduction and can be applied to counting homomorphisms. The final tool is the classical theorem of Epifanov showing that any plane graph can be reduced to a single vertex and no edges by extended series-parallel reductions and Delta-Wye transformations. This last sort of transformation is available to us in the case of exactly triply regular association schemes. The paper includes open problems and directions for future research.

Tightening Curves on Surfaces Monotonically with Applications

We prove the first polynomial bound on the number of monotonic homotopy moves required to tighten a collection of closed curves on any compact orientable surface, where the number of crossings in the curve is not allowed to increase at any time during the process. The best known upper bound before was exponential, which can be obtained by combining the algorithm of De Graaf and Schrijver [ J. Comb. Theory Ser. B , 1997] together with an exponential upper bound on the number of possible surface maps. To obtain the new upper bound, we apply tools from hyperbolic geometry, as well as operations in graph drawing algorithms—the cluster and pipe expansions—to the study of curves on surfaces. As corollaries, we present two efficient algorithms for curves and graphs on surfaces. First, we provide a polynomial-time algorithm to convert any given multicurve on a surface into minimal position. Such an algorithm only existed for single closed curves, and it is known that previous techniques do not generalize to the multicurve case. Second, we provide a polynomial-time algorithm to reduce any k -terminal plane graph (and more generally, surface graph) using degree-1 reductions, series-parallel reductions, and Δ Y -transformations for arbitrary integer k . Previous algorithms only existed in the planar setting when k ≤ 4, and all of them rely on extensive case-by-case analysis based on different values of k . Our algorithm makes use of the connection between electrical transformations and homotopy moves and thus solves the problem in a unified fashion.

A Systematic Method for Finding the Input Impedance of Two-Terminal Networks

ABSTRACTWhen a network is a simple ladder network, its input impedance can be obtained simply using series–parallel reduction techniques. If there are bridging elements, such as bridged-T network or Wheatstone bridge, the network cannot be solved just by these techniques. Then one has to take the help of star–delta transformation. A systematic method is given for obtaining the input impedance of any complicated network. We shall deal with resistive networks first, and then all-L and all-C networks. Finally, more complex RLC networks in jw-domain are covered.

System Reliability Evaluation for Imperfect Networks Using Polygon-to-Chain Reduction

The purpose of this paper is to propose a computational technique for evaluating the reliability of networks subject to stochastic failures. In this computation, a mathematical model is provided using a technique which incorporates the effect of the factoring decomposition theorem using polygon-to-chain and series-parallel reductions. The algorithm proceeds by identifying iteratively one of seven polygons and when it is discovered, the polygon is immediately removed and replaced by a simple chain after having changed the individual values of the reliability of each edge and each node of the polygon. Theoretically, the mathematical development follows the results presented by Satyanarayana & Wood and Theologou & Carlier. The computation process is recursively performed and less constrained in term of execution time and memory space, and generates an exact value of the reliability.

Complex System Reliability Optimisation: A Multi-Criteria Approach

The optimal allocation of reliability to the components of complex systems to maximise their reliability is posed as multi-criteria optimisation. The minimum cut-sets leading to series-parallel reduction of such systems were constituted into criteria and their reliability maximised while minimising cost of improving the systems reliability. Consequently, the system reliability expression is made redundant, which simplifies the problem. The resultant nonlinear optimisation model was solved by the Weighted Sum method for the Pareto optimal component reliability values. The model was applied to a life support system. The results show that higher components/ systems reliability can be achieved using the approach.

A new simulation method based on the RVR principle for the rare event network reliability problem

In this paper we consider the evaluation of the well known Open image in new window-network unreliability parameter by means of a new RVR Monte-Carlo method. This method is based on series-parallel reductions and a partitioning procedure using pathsets and cutsets for recursively changing the original problem into similar ones on smaller networks. By means of several experimental results, we show that the proposed method has good performances in rare event cases and offers significant gains over other state-of-the-art variance reduction techniques.

Timing analysis for full-custom circuits using symbolic DC formulations

Successful analysis of high-speed integrated circuits requires accurate delay computation. A number of delay models have been developed; however, none can claim to be truly robust in the face of large channel-connected regions (CCRs) with input "exclusivity" constraints. A good circuit-level delay model should: 1) consider input exclusivity constraints; 2) handle a wide range of circuit structures; and 3) have a robust underlying framework that can be applied independent of the actual device model. We present a symbolic timing analysis tool that aims to address these three goals. It uses algebraic decision diagrams (ADDs) to estimate delay within a CCR as a function of its inputs while easily handling Boolean input constraints. It starts with a simple linear resistor model for transistors and from there apply various heuristics to improve the delay estimation without altering the symbolic algorithms. It analyzes delay with simple series-parallel reduction when possible and use symbolic matrix techniques to handle more complex circuit structures. The effectiveness of our approach is demonstrated on circuits from industry used in the Alpha 21264 and 21364 instead of the usual International Symposium on Circuits and Systems (ISCAS) or Microelectronics Center of North Carolina (MCNC) benchmarks. Our delay estimates are within 10% of simulation program with integrated circuits emphasis (SPICE) for over 90% of the circuits we simulated. This difference can translate into significant savings in manpower by avoiding the need to verify many unrealizable worst case conditions with other, more costly, simulation techniques

More Forbidden Minors for Wye-Delta-Wye Reducibility

A graph is $Y\Delta Y$ reducible if it can be reduced to isolated vertices by a sequence of series-parallel reductions and $Y\Delta Y$ transformations. It is still an open problem to characterize $Y\Delta Y$ reducible graphs in terms of a finite set of forbidden minors. We obtain a characterization of such forbidden minors that can be written as clique $k$-sums for $k=1, 2, 3$. As a result we show constructively that the total number of forbidden minors is more than 68 billion up to isomorphism.

Series-parallel reductions in Monte Carlo network-reliability evaluation

Monte Carlo simulation appears to be very useful in the evaluation of K-terminal-reliability of large communication systems because the exact algorithms are extremely time consuming. This paper shows that the well-known series-parallel reductions can be incorporated in the recursive variance reduction simulation method, leading to a more efficient estimator, as demonstrated by experimental results.

On Spin Models, Triply Regular Association Schemes, and Duality

Motivated by the construction of invariants of links in 3-space, we study spin models on graphs for which all edge weights (considered as matrices) belong to the Bose-Mesner algebra of some association scheme. We show that for series-parallel graphs the computation of the partition function can be performed by using series-parallel reductions of the graph appropriately coupled with operations in the Bose-Mesner algebra. Then we extend this approach to all plane graphs by introducing star-triangle transformations and restricting our attention to a special class of Bose-Mesner algebras which we call exactly triply regular. We also introduce the following two properties for Bose-Mesner algebras. The planar duality property (defined in the self-dual case) expresses the partition function for any plane graph in terms of the partition function for its dual graph, and the planar reversibility property asserts that the partition function for any plane graph is equal to the partition function for the oppositely oriented graph. Both properties hold for any Bose-Mesner algebra if one considers only series-parallel graphs instead of arbitrary plane graphs. We relate these notions to spin models for link invariants, and among other results we show that the Abelian group Bose-Mesner algebras have the planar duality property and that for self-dual Bose-Mesner algebras, planar duality implies planar reversibility. We also prove that for exactly triply regular Bose-Mesner algebras, to check one of the above properties it is sufficient to check it on the complete graph on four vertices. A number of applications, examples and open problems are discussed.

Partial factoring: an efficient algorithm for approximating two-terminal reliability on complete graphs

An efficient network reliability approximation algorithm for two-terminal undirected complete graphs is presented. The method recursively applies a factoring theorem of network reliability in conjunction with series-parallel reliability-preserving reductions. After each pivot, one of the resulting subproblems is further factored, while the other is approximated. The final approximate solution is given in terms of an upper and a lower bound. In the worse case, the algorithm requires O( mod V mod /sup 2/ log mod V mod ) time and O( mod V/sup 2/ mod ) space. For 128-node complete graphs, the method requires less than 16 s on an IBM AT personal computer. The algorithm's mean error bound is both theoretically and empirically analyzed. The mean difference between the upper and lower bounds is guaranteed to be less than 10/sup -14/ for component reliabilities uniformly distributed between 0.99 and 1.00. Empirically, this difference is always less than 10/sup -17/. >

Block diagram network transformation

Block diagram networks consisting of linear unidirectional elements form the basis for this simple and direct method of transforming and reducing networks for analysis. Particularly applicable to servomechanisms and control circuits, this method is similar in approach to Y-delta transformation and series-parallel reduction for solving ordinary networks.