Series-connected Capacitors Research Articles

A D-Band Differential Amplifier With Cross-Couple of Series-Connected Capacitor and Transmission Line-Based Dual-Frequency G max-Core

A D-Band Differential Amplifier With Cross-Couple of Series-Connected Capacitor and Transmission Line-Based Dual-Frequency <i>G</i> _max-Core

An Effective Power Improving Method of Magnetic Field Energy Harvesters Using a Series-Connected Capacitor for Wireless Sensors in Smart Grids

An Effective Power Improving Method of Magnetic Field Energy Harvesters Using a Series-Connected Capacitor for Wireless Sensors in Smart Grids

Comments on “An Effective Power Improving Method of Magnetic Field Energy Harvesters Using a Series-Connected Capacitor for Wireless Sensors in Smart Grids”

Comments on “An Effective Power Improving Method of Magnetic Field Energy Harvesters Using a Series-Connected Capacitor for Wireless Sensors in Smart Grids”

A hybrid DC-DC modular multilevel converter with capacitors parallel connectivity for arm energy balancing

The integration of renewable energy sources in Medium-/High-voltage DC grids has called up continuous research to develop DC-DC conversion systems. This paper presents a hybrid modular multilevel DC-DC converter topology which successfully overcomes the issue of capacitors voltage imbalance during DC-DC conversion. In the proposed topology, single MMC leg is employed with half-bridge submodules in the upper arm and full-bridge submodules in the lower arm along with soft-switched high-voltage valves. The proposed hybrid modular multilevel converter has inherited arm energy equalization with the help of the parallel connectivity of involved arms’ capacitors. During the equalization period, the series-connected upper arm capacitors are connected in parallel to the series-connected lower arm capacitors to transfer the energy between the involved arms which results in operating with balanced capacitors voltages. The proposed modular DC-DC converter is a bidirectional converter which allows power flow from high-voltage side to low-voltage side and vice versa, i.e., it can be operated successfully as a DC transformer. The operational concept of the proposed configuration, control strategy, and parameters design are presented. Simulation results are presented along with experimental results of a scaled-down prototype to validate the proposed approach. Simulation and experimental results show the viability of the suggested approach.

Investigation of time domain measurement of electrochemical impedance spectrum in low frequency range for lithium-ion batteries using preset equivalent circuit model

A time domain measurement technique using a preset equivalent circuit model consisting of many series-connected resistor and capacitor parallel elements was examined as a measurement method of the electrochemical impedance spectrum of a lithium-ion battery excluding the apparent impedances from open circuit voltage change in the low frequency range. At first, a comprehensive experimental study was carried out to determine the standard condition of the applied signal suitable for this technique. It was established that an impedance spectrum from several tens of microhertz to several tens of millihertz can be accurately measured by selecting a proper, small rate and long duration constant current charge or discharge as the applied signal. Next, impedance spectra excluding the apparent impedances from open circuit voltage change were measured under various conditions using this technique, and basic characteristics of the impedances of the solid state diffusion processes of lithium that exist in the corresponding low frequency range were investigated. It was revealed that the impedance spectrum excluding the apparent impedances from open circuit voltage change in the low frequency range, from several tens of microhertz to several tens of millihertz, can be reasonably separated into two finite length Warburg impedances that can be clearly characterized by difference in their diffusion time constant values and in the state of charge dependence of their diffusion resistances. An Arrhenius type temperature dependence was confirmed for both of their diffusion resistances.

Threshold Voltage Instability Measurement Circuit for Power GaN HEMTs Devices

The p-GaN gate-based gallium nitride (GaN) high electron mobility (HEMTs) devices are preferred to achieve normally-off operation in power electronic applications. However, this type of device suffers from threshold voltage instability. That instability is typically characterized using a curve tracer. The curve tracer is unable to provide shorter pulse width lesser than 500 µs. This drawback restricts the characterization of the device operating at a higher frequency. In order to address this issue, a half-bridge circuit with a series-connected capacitor is proposed. The half-bridge allows for achieving shorter pulse width, whereas the capacitor provides transient current. Using these two features of the circuit, an EPC2014C device is characterized, and the instability in threshold voltage is reported.

An Interleaved High Step-Up DC/DC Converter-Based Three-Winding Coupled Inductors With Symmetrical Structure

This paper proposes an interleaved high step-up converter based on three-winding coupled inductor (TW-CI) with symmetrical structure. By utilizing the TW-CI along with a voltage multiplier cell, the proposed converter achieves high power transfer ability as well as minimized voltage stress across power switches and diodes. The converter has significantly improved the voltage gain by integrating two TW-CIs with the passive clamp circuit. The leakage inductor energy of the TW-CI is recycled to improve the voltage gain and efficiency while facilitating the soft switching condition for the power switches. Additionally, the voltage stress across the power switches is decreased with the help of the clamping capacitors. Therefore, low-voltage-rated semiconductors with small on-resistance can be chosen which reduce conduction losses and improve the overall performance. Moreover, two series-connected capacitors of the primary side are introduced, which effectively balance the voltage between the power switches and the capacitors during steady and dynamic states. Finally, a 400W experimental prototype with 24V-400V is built to is verify the accuracy of proposed converter.

A Generalized Multilevel Inverter With Extended Linear Modulation Range and Instantaneously Balanced DC-Link Series Capacitors for an Induction Motor Drive

The voltage drift control of series-connected capacitors across a single dc-link is the major challenge for a multineutral point-clamped (NPC) converter. This drifting is caused due to uneven currents drawn from the neutral points (NPs) during the PWM operation. This work presents the working principle of instantaneous voltage control of “ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$n$ </tex-math></inline-formula> ” dc-link series-connected capacitors for an induction machine load. The mechanism of instantaneous voltage balancing is realized by ensuring zero instantaneous currents at each dc-link NP. To get zero instant currents at a dc-link NP branch, the phase terminals tapping on the dc-link are manipulated with the help of cascaded hybrid bridges (CHBs). Charge balancing of CHB capacitors is also taken care of by proper utilization of pole voltage redundancies. The detailed results are presented for a small-scaled inverter (nine-level) with three NPs (four dc-link capacitors). The simulation and experimental results reflect the capability and limitations of such inverters. The results are presented at all modulation indexes operated under low-power-factor (LPF) and high-power-factor (HPF) load conditions. It is found that the linear modulation range (LMR) can be increased to full base speed even for an HPF load.

A Multilevel Inverter With Inherent Common Coupling Point Voltage Balancing of Stacked Capacitors Across a Single DC-Link for Induction Motor Drives

In this article, a nine-level multilevel topology is proposed by stacking of low voltage basic inverter cells and then cascading with H-bridges. The dc-link is split into four equal halves by series-connected capacitors from a common dc-link. Three common coupling points (CCPs) are formed due to the stacking of four capacitors, which are connected across the dc-link. The CCP voltage balancing is ensured by drawing or injecting zero instantaneous currents from each of these points at any instant. A six-phase symmetrical IM is used to generate equal and opposite instantaneous phase currents by applying exactly equal and opposite phase voltages for two opposite phases from the six-phase inverter. Simultaneously, the capacitor voltage balancing of H-bridge inverter cells is also achieved by proper selection of redundancies from the available pole voltage redundancies. The concept is verified with a nine-level inverter laboratory prototype, which consists of a five-level stacked inverter, and followed by two low voltage cascaded H-bridge inverters in each phase. Detailed experimental results of steady-state and transient conditions are included to validate the proposed scheme.

Capacitor Voltage Balancing Control for a Novel 5-Level Dual Active Bridge Converter

Multilevel technology is an attractive solution to increase the cost effectiveness and power density of dc solid state transformers. In this article, a novel five-level (5L) dual active bridge (DAB) converter topology is proposed. By stacking two neutral-point-clamped (NPC) converters at the primary side, the proposed topology could quadruple the input dc-bus voltage of a conventional two-level (2L) DAB converter. Besides, by analyzing the working principle of the 5L-DAB converter, a voltage balancing control method is carried out. With the aid of the voltage balancing method, voltages of the four series-connected dc-bus capacitors in the 5L-DAB converter can be actively balanced, guaranteeing safe operation voltage for all the semiconductor switches. After that, the operation range of the proposed voltage balancing method is derived by theoretical analysis. Finally, the performance of the proposed converter topology and voltage balancing method have been verified by experimental results.

A Multilevel Inverter for Instantaneous Voltage Balancing of Single Sourced Stacked DC-Link Capacitors for an Induction Motor Load

This article proposes a novel nine-level multilevel inverter topology with an instantaneous voltage balancing scheme of stacked dc-link capacitors for an induction motor (IM) drive application. Three neutral points (NPs, terminal joints of four series-connected capacitors) across a single dc-link are balanced instantaneously (within a sampling interval) by ensuring zero current at the NPs. The proper selection of pole voltage from the redundancies provides zero current at any NP during the pulsewidth modulation operation under a steady-state and transient operation. A five-level stacked inverter and three cascaded hybrid-bridge (CHB) inverter cells are used in each phase. Along with the balancing of dc-link capacitors, CHB capacitors’ voltage balancing is also achieved using the pole voltage redundancies at all modulation indexes for all power factor and load. It is also possible to increase more number of levels using more low-voltage switches, and a generalized form of the topology is presented. The concept is validated using a laboratory-developed nine-level inverter with a three-phase IM load, operated under “V/ <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> ” control. The detailed experimental results for the steady and transient condition, simulation studies for switching loss, and harmonic content in the phase voltage are also presented.

A High-Power Terahertz Source Over 10 mW at 0.45 THz Using an Active Antenna Array With Integrated Patch Antennas and Resonant-Tunneling Diodes

We propose a compact, high-power, and high-directivity surface-emitting terahertz (THz) source based on an array of active antennas with integrated patch antennas and resonant-tunneling diodes (RTDs). An array configuration of active antennas, each with an integrated patch antenna and two RTDs and coupled by microstrip lines, enables spatial power combining and improves directivity through coherent oscillation. We confirmed a maximum radiation power of 11.8 mW in a prototype 6 × 6 array at an oscillation frequency of 0.45 THz. Parasitic oscillation at low frequencies was suppressed by use of a bias stabilization circuit consisting of series-connected resistors and capacitors, and the dc to RF efficiency of this device was estimated to be approximately 1%. The radiant intensity of 210 mW/sr and the 3-dB beamwidth of 13° for the measured 6 × 6 array confirmed that directivity was improved by coherent oscillation based on mutual injection locking. The directivity of the patch antenna capable of surface emission can be controlled only by the number of antennas, even if there is no secondary radiator, such as an Si lens. The obtained results suggest that RTDs are promising as practical THz sources for realizing applications of THz imaging and 6G communication.

TRANSIENT ANALYSIS OF ACTIVE-CAPACITIVE CIRCUITS WHEN CAPACITORS ARE CONNECTED IN SERIES

Active-capacitive and inductive-capacitive circuits with series connection of capacitors are widely used in the electric power industry to compensate for reactive power. In traction power supply systems for railways electrified with alternating current, compensation units perform two tasks: under heavy load, they maintain a given railway throughput, and under low load, they reduce power losses in the traction network. Therefore, the installation of compensation in the traction network must be at least two-stage, i.e. have two reactive power values and, accordingly, two capacitance values. The value of reactive power in such installations is regulated in steps by switching individual sections of capacitors, which are connected in series. When switching capacitors in series, previously unknown specific transients can occur. They cause significant overvoltages on the capacitors. It is shown that in some cases the calculation of transient processes in active-capacitive circuits with capacitors connected in series using the well-known classical method gives results that differ from the actual values. The purpose of the article is to provide a previously unknown theoretical basis for calculating transient processes in electrical circuits containing series-connected capacitors using the example of active-capacitive DC circuits. The studies carried out are of practical importance, since in modern electrical installations, thyristor switches are used as switching equipment, in which the shunting of one capacitor in the compensating installation occurs at the maximum voltage on the operating capacitor. In this case, overvoltages exceeding the assumed values ​​are possible, in the limit up to double the amplitude value of the supply voltage. A theoretical substantiation of this phenomenon is given by the example of the analysis of the transient process in an active-capacitive circuit with two consecutively connected capacitors.

A Nine-Level Inverter With Single DC-Link and Low-Voltage Capacitors as Stacked Voltage Sources With Capacitor Voltage Control Irrespective of Load Power Factor

This paper proposes a multilevel inverter topology with a single DC-link and series-connected capacitors as stacked voltage sources for multilevel voltage generation. The voltage deviation of a DC-link capacitor will occur whenever a phase terminal connects to the balanced neutral points (NPs: terminal joints of DC-link capacitors). On the contrary, if the voltage of a DC-link capacitor deviates from the nominal voltage, the same phase currents can be utilised to balance these neutral points. This new technique is being proposed for the first time in literature. Any voltage disturbance of the DC-link capacitors is balanced using the motor phase currents, irrespective of load power factor and modulation indices. For the balanced neutral points, whenever a phase connects to a neutral point, the other phase terminal tapping positions are varied on the DC-link to establish <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$i_{A}+i_{B}+i_{C}=0$</tex-math></inline-formula> for that neutral point. The pole voltage level variation at motor phase terminals is undisturbed by adding extra cascaded H-bridges (CHBs) at each phase leg. The voltages of CHB capacitors are controlled conventionally by inverter pole voltage redundancies. The detailed experimental results for open-loop V/ <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> and closed-loop field-oriented control on an induction motor are presented using a nine-level laboratory prototype.

A 0.007 mm2 0.6 V 6 MS/s Low-Power Double Rail-to-Rail SAR ADC in 65-nm CMOS

A 0.007mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> 0.6V 6MS/s 10b double rail-to-rail input range SAR ADC is implemented in 65-nm technology. The extended input range broadens the applications of the low-power SAR ADCs such as compute-in-memory. The proposed ADC occupies less area since it only needs additional two series-connected capacitors and a differential-difference comparator for double rail-to-rail operation. The set-and-down operation reduces the input-referred noise of the comparator by over ten times than complementary switching. The novel metal-insulator-metal and metal-oxide-metal capacitor hybrid cap-DAC architecture minimize the gain error of ADC. The prototype achieves SNR of 53.90-dB, SNDR of 52.12-dB, and SFDR of 60.39-dB, power of 12.98- μW, and FoM of 6.6-fJ/conv.-step.

Active emulation circuits of fractional-order memristive elements and its applications

The paper investigates the effect of fractional-order parameters on the memristive features such as hysteresis lobe area, the number of pinched points, and their coordinates. In addition, the series-connected fractional-order inductor and capacitor with memristive elements are discussed where the coordinates of the pinched point move away from zero points as α changes. The second-and third-order memristive elements are studied, introducing more than one pinched point with a zero-crossing point in the i - v plane. Four different memristor⧹inverse memristors emulators are presented based on several active building blocks. The voltage- and current-controlled emulators are introduced employing the second-generation current conveyor (CCII) and analog multiplier (AM) with generalized impedances. Those emulators are employed to realize the higher-order memristive elements by adding another AM. Switched memristive emulation circuit is also presented based on the extra-x current controlled conveyor (EXCCCII) and two switches. The last introduced memristive emulator consists of one current feedback operational amplifier (CFOA) and two BJT transistors. The introduced circuitry is simulated to validate the presented circuits using PSPICE simulations, and one of them is validated experimentally. Finally, the second-order memristor is employed in Chua’s chaotic oscillator as an application.

Capacitors Voltage Ripple Complementary Control on Three-Level Boost Fed Single-Phase VSI With Enhanced Power Decoupling Capability

Power decoupling is always a strong desire for single-phase voltage source inverter (VSI) due to the inherent double-line (2ω) frequency ripple caused by the instantaneous power unbalance between dc- and ac-side. The existing solutions either apply a large capacitor or employ a small power converter to compensate it, which inevitably increases the system cost and control complexity. To overcome these drawbacks, this article performs the transient modeling analysis and it reveals that 2ω frequency power component in the converter achieves minimum value when the inductor current ripple is minimized. A novel capacitors' voltage ripple complementary control algorithm based on three-level boost fed single-phase VSI is proposed. By mitigating the 2ω power component from the inductor and redistributing the stored energy between two intermediate series-connected capacitors, the oscillating power is absorbed with notably eliminated input current ripple and significantly reduced dc-link voltage ripple. Thus, the good power quality of both dc- and ac-side is guaranteed. Furthermore, the total capacitance requirement is minimized under the given dc-link ripple tolerance without any more electric stress increment and lifetime reduction. Simulation and experiment results verify the theoretical analysis and proposed control method. It is promising in applications, where both input current ripple is strictly limited and ac output voltage quality is highly required with small dc-link capacitance.

Improved Coordinated Control Approach for Evolved CCC-HVDC System to Enhance Mitigation Effect of Commutation Failure

The evolved capacitor commutated converter (ECCC), embedded with anti-parallel thyristors based dual-di-rectional full-bridge modules (APT-DFBMs), can effectively reduce commutation failure (CF) risks of line-commutated con-verter-based high voltage direct current (HVDC) and improve the dynamic responses of capacitor-commutated converter-based HVDC. This paper proposes an improved coordinated control strategy for ECCC with the following improvements: 1 under normal operation state, series-connected capacitors can accelerate the commutation process, thereby reducing the overlap angle and increasing the successful commutation margin; 2 under AC fault conditions, the ability of ECCC to mitigate the CF issue no longer relies on the fast fault detection, since the capacitors inside the APT-DFBMs can consistently contribute to the commutation process and further reduce the CF probability; 3 the inserted capacitors can output certain amount of reactive power, increase the power factor, and reduce the required reactive power compensation capacity. Firstly, the proposed coordinated control approach is presented in detail, and the extra commutation voltage to mitigate the CFs provided by the proposed control approach and an existing approach is compared. Secondly, the mechanism of the improved control approach to accelerate commutation process and improve the power factor is analyzed theoretically. Finally, the detailed electromagnetic transient (EMT) simulation in PSCAD/EMTDC is conducted to validate the effectiveness of the proposed coordinated control. The results show that the proposed approach can present a further substantial improvement for ECCC, especially enhancing the CF mitigation effect.

High-Gain Switched-Capacitor DC-DC Converter With Low Count of Switches and Low Voltage Stress of Switches

This paper presents a novel concept of a high-voltage-gain DC-DC converter. The converter is made up of switched capacitors and passive resonant branches. A significant reduction in the count of switches and low voltage stress on the switches is achieved in this proposed converter topology, in comparison to that of a classical SC series-parallel converter. It is essential from the cost, volume, and efficiency of the converter standpoint. The reduction in the count of switches is threefold. The highest voltage stress on the switches depends on the output voltage and is decreased in the proposed converter as well, as the output voltage is divided into two series-connected capacitors. The presented results demonstrate the operation of the converter with the use of resonant branches, its switching strategies, voltage stresses of switches, efficiency, voltage gain, and output voltage regulation as well as the zero-voltage switching (ZVS) operation. The paper also presents novel issues related to analytical loss modeling, extended concepts of topology, converter start-up, and operation during transient states. The demonstrated concept of the converter, the analytical discussion and its design, as well as the experimental setup and results clearly demonstrate the optimization achievements.

Topology and Voltage-Balance Control of a Single-Phase Active Neutral Point Clamped Seven-Level Inverter

This article proposed a single-phase active neutral point clamped seven-level (SANPC-7L) inverter topology with only eight power switches and three dc-link capacitors. Compared with the existing single-phase seven-level inverters, the quantity of power switches and voltage stresses across them are both reduced. Modulation logic expression of every switch is derived based on the Karnaugh map technique. Like the existing counterparts with three series-connected dc-link capacitors, there is a severe capacitor voltage imbalance issue. This issue is hard to address as there are no redundant switching states that can be selected to balance the dc-link capacitor voltages. This article gives a comprehensive analysis on the capacitor voltage imbalance issue. It indicates that the over charge or discharge of the middle capacitor voltage is the root cause of this issue, while the upper and lower capacitor voltages can be automatically balanced. To overcome this issue, a variable-reference voltage-balance control method is used to enable a three-level voltage waveform to appear in every switching period, and thus the middle capacitor voltage can be controlled at 1/3 of the dc-link voltage. Both the simulation and experimental results have been presented to verify the proposed topology with the variable-reference voltage-balance control strategy.