Serial Powering Scheme Research Articles

Serial powering characterisation for the CMS Inner Tracker at the High Luminosity LHC

The CMS tracking system will be completely replaced in order to operate in the extreme conditions of the High Luminosity LHC. The new tracker will consist of two main subdetectors: the Inner Tracker, containing pixel modules, and the Outer Tracker, consisting of strip and macro-pixel modules. In the Inner Tracker, silicon sensors will be read out by the CMS Readout Chip (CROC). The chip, built in 65 nm CMOS technology, is able to withstand high radiation doses (500 Mrad) and hit rates (3 GHz/cm2 on the innermost tracking layer) during operation. Moreover, it must handle a fine sensor granularity (2500 µm2 pixels) and operate at low detection thresholds (1000 e-). The Inner Tracker will make use of the serial powering scheme to provide the ∼60 kW required by ∼4000 modular units. The Shunt-LDO (SLDO) regulator is the part of the CROC responsible for providing the power by draining a constant current in time, independently of the chip power consumption. Tests performed with Single Chip Cards (SCC) in serial configurations are reported in this paper.

Overview of the ATLAS ITk pixel detector

In the high-luminosity era of the Large Hadron Collider, the instantaneous luminosity is expected to reach unprecedented values, resulting in up to 200 proton-proton interactions per bunch crossing. To cope with the resulting increase in occupancy, bandwidth and radiation damage, the ATLAS Inner Detector will be replaced by an all-silicon system, the Inner Tracker (ITk), where the innermost part will consist of a pixel detector with about 14 m2 of active area. Several silicon sensor technologies will be employed in order to deal with the strict requirements in terms of radiation hardness, power dissipation and production yield. Prototype modules assembled with RD53A readout chips are being built to evaluate their production rate, thermal- and electrical performance, before- and after irradiation. In addition, a novel serial powering scheme will be implemented in the ITk pixel detector, which will help to reduce the material budget of the detector inside the active detector volume as well as power dissipation. Multiple system-level tests are being done with serial powering of pixel modules. The latest development of prototype modules, serial powering tests, and procedures of integration of modules and electrical services are presented.

Prototyping serial powering for the ATLAS ITk pixel detector

The high luminosity upgrade for the LHC at CERN requires a complete overhaul of the current inner detectors of ATLAS and CMS. A serial powering scheme has been chosen to cope with the constraints of the new pixel detectors. A prototype stave consisting of up to 8 quad modules, based on the new readout chips developed by the RD53 collaboration in 65 nm CMOS technology, RD53A and ITkPixV1, has been set up in Bonn. This contribution covers the results obtained with RD53A modules and presents first measurements with a full ITkPixV1.1 serial powering chain.

Characterization and verification of the Shunt-LDO regulator and its protection circuits for serial powering of the ATLAS and CMS pixel detectors

The Shunt-LDO regulator has been integrated in the ATLAS and the CMS pixel detector RD53 front-end chip to implement the serial powering scheme which both experiments have chosen as the baseline option for the HL-LHC upgrade. The performance of the integrated regulators has been characterized and specific design challenges have been identified which are related to layout parasitics and shallow trench isolation (STI) stress effects. In addition the functionality of circuits which address crucial system level aspects like the protection against overvoltage/overload has been verified.

The CMS Inner Tracker electronics system development

A new Silicon Tracker will be built for the phase-2 upgrade of the CMS experiment. The innermost part, called the Inner Tracker, will be featuring high-granularity pixelated silicon sensors of 2500 µm2 and will need to cope with the unprecedented radiation levels of 1.9 Grad and 3.5 × 1016 neq/cm2 fluence and particle hit rates of 3.2 GHz/cm2. The pixel electronics system is based on innovative solutions such as a radiation hard pixel ASIC, the novel serial powering scheme used to power up to 12 detector modules in series and advanced technologies for the high bandwidth readout system based on electrical light-weight readout links of 1.28 Gbps, electrical to optical conversion as close as possible to the detector modules and back-end boards each one capable of receiving an aggregated data bandwidth of 190 Gbps. The recently optimised design of the CMS Inner Tracker electronics system will be presented in this contribution.

Development of a charge pump for sensor biasing in a Serial Powering scheme for the ATLAS pixel detector upgrade

CMOS monolithic pixel detector technology is one of the options considered for the outer layer of an upgraded ATLAS pixel detector in 2026. In this upgrade pixel detector modules will be powered in series by a constant current source to reduce power losses and material budget. On-chip shunt regulators generate the local 1.8 V supply voltage from the input current to provide power to the integrated circuits. The sensor bias for monolithic sensors is often limited and not sufficiently large to allow a common bias for all sensors in the serial powering chain. In this paper, we give an introduction to the serial powering strategy for CMOS detectors with emphasis on the design and simulation results of a regulated charge pump circuit for sensor biasing. Two prototypes operating with a pumping frequency of 640 MHz, one with 6-stages and one with 19-stages, were designed and fabricated in a modified TowerJazz 0.18 μm CMOS imaging technology to provide negative bias down to − 6 V and − 20 V, respectively. Simulation results demonstrate good performance of the charge pump circuit which could be used to bias the CMOS sensor.

A serial powering pixel stave prototype for the ATLAS ITk upgrade

One of the main challenges for the ATLAS ITk Phase II Pixel upgrade is low-mass efficient power distribution for detector modules. This requires a powering scheme alternative to the parallel (direct) powering which is currently used. A serial powering scheme has been chosen as the baseline for the ITk pixel system. A serially powered pixel detector prototype has been built with all the components that are needed for current distribution, data transmission, bypassing and redundancy in order to prove the feasibility of implementing serial powering scheme in the ITk. Detailed investigations of the electrical performance of the detector prototype equipped with FE-I4 quad modules have been made with the help of the USBpix3 readout system that has been developed in Bonn.

Performance evaluation of a serially powered pixel detector prototype for the HL-LHC

Efficient and low mass power distribution presents a challenge for vertex and tracking detectors at the HL-LHC . Different approaches have been considered to transmit power at low current and high voltage. This paper presents the serial powering scheme proposed as baseline for the ATLAS and CMS pixel detectors at the HL-LHC . A serially powered detector prototype with six pixel modules has been built, featuring all elements needed for current distribution, redundancy, data transmission, and sensor biasing. Results of the characterisation of the prototype in standard operating conditions as well as in more challenging scenarios including increased digital activity are presented.

Ongoing studies for the control system of a serially powered ATLAS pixel detector at the HL-LHC

In terms of the phase-2 upgrade of the ATLAS detector, the entire inner tracker (ITk) of ATLAS will be replaced. This includes the pixel detector and the corresponding detector control system (DCS). The current baseline is a serial powering scheme of the detector modules. Therefore a new detector control system is being developed with emphasis on the supervision of serially powered modules. Previous chips had been designed to test the radiation hardness of the technology and the implementation of the modified I2C as well as the implementation of the logic of the CAN protocol. This included tests with triple redundant registers. The described chip is focusing on the implementation in a serial powering scheme. It was designed for laboratory tests, aiming for the proof of principle. The concept of the DCS for ATLAS pixel after the phase-2 upgrade is presented as well as the status of development including tests with the prototype ASIC.

Progress and advances in Serial Powering of silicon modules for the ATLAS Tracker Upgrade

Future detector systems will face technical difficulties with the supply of electrical power to a multitude of sub-detectors. The Serial Powering (SP) scheme is an elegant solution which leads to a great reduction in cable mass, whilst increasing efficiency and reducing cost. In recent years, substantial developments in SP have been made by the ATLAS Tracker Upgrade Community. Initial demonstrator modules and supermodules (known as Staves) used the ABCD chip, with shunt regulators made from discrete components. Continuous development of the SP architecture has led to shunt regulation within the latest ABCN-25 ASICs themselves. From a system point of view, studies of protection schemes and current sources have advanced greatly. We report recent progress, including first results from a serially powered Stavelet using the ABCN-25 chip.

A serial powering scheme for the ATLAS pixel detector at sLHC

Powering concepts, such as serial powering and DC-DC conversion, are in development for the silicon trackers at sLHC to achieve an efficient power distribution with a minimum volume of cables. This paper will describe the serial powering scheme developed for the upgraded ATLAS pixel detector, with focus on the scheme architecture and on the main components involved: the Shunt-LDO regulator and the protection scheme. Issues connected to system aspects will be discussed, and the advantages in terms of material reduction provided by the proposed serial powering scheme will be presented.

Switched capacitor DC-DC converter ASICs for the upgraded LHC trackers

The High Luminosity Upgrade of the ATLAS Inner Tracker puts demanding requirements on the powering system of the silicon strip detector modules due to 10-fold increase of the channel count compared to the existing SemiConductor Tracker. Therefore, new solutions for the powering scheme must be elaborated. Currently two possible approaches, the serial powering and the parallel powering scheme using the DC-DC conversion technique, are under development. This paper describes two switched capacitor DC-DC converters designed in a 130 nm technology. For the optimized step-down converter, foreseen for the parallel powering scheme, power efficiency of 97% has been achieved, while for the charge pump, designed for the serial powering scheme, power efficiency of 85% has been achieved.

Serial Powering of Silicon Strip Modules for the ATLAS Tracker Upgrade

Serial Powering is a powering solution to the issues of costs, difficulties and inefficiencies associated with the cabling of large detector systems. This powering option is being actively pursued by the ATLAS Tracker upgrade community. Demonstrator supermodules have been produced using the ABCD chip from the present ATLAS SCT together with serial powering circuitry built from commercial components. Two six modules stave systems have been built, and construction of a third stave consisting of thirty modules has been designed and construction is in progress. Recent results from these supermodules have been discussed. New ASICs have been designed that include elements of the serial powering scheme, and studies of system issues are ongoing. These developments and their application to the next demonstrator supermodule will be outlined.