Serial Memories Research Articles

A Serial Memory by Quantum-Dot Cellular Automata (QCA)

Quantum-dot Cellular Automata (QCA) has been widely advocated as a new device architecture for nanotechnology. QCA systems require extremely low power, together with the potential for high density and regularity. These features make QCA an attractive technology for manufacturing memories in which the paradigm of memory-in-motion can be fully exploited. This paper proposes a novel serial memory architecture for QCA implementation. This architecture is based on utilizing new building blocks (referred to as tiles) in the storage and input/output circuitry of the memory. The QCA paradigm of memory-in-motion is accomplished using a novel arrangement in the storage loop and timing/clocking; a three-zone memory tile is proposed by which information is moved across a concatenation of tiles by utilizing a two-level clocking mechanism. Clocking zones are shared between memory cells and the length of the QCA line of a clocking zone is independent of the word size. QCA circuits for address decoding and input/output for simplification of the Read/Write operations are discussed in detail. An extensive comparison of the proposed architecture and previous QCA serial memories is pursued in terms of latency, timing, clocking requirements, and hardware complexity.

Multiple Number and Letter Comparison: Directionality and Accessibility in Numeric and Alphabetic Memories

In 3 experiments, subjects made comparativejudgments on a set of 2 numbers or letters, 3 numbers or letters, or 5 numbers or letters. Numeric and alphabetic serial order memories were contrasted. Three aspects of serial order memory processes were identified: computational complexity, directionality, and accessibility. Computational complexity is the number of algorithmic steps involved in identifying a target. Directional bias is measured as the speed differences in identifying serial targets of equal computational complexity in a stimulus array. Memory accessibility is measured as the numeric and alphabetic serial position effects. Subjects had a slight directional bias favoring backward ordering for single digits but no bias in 2-digit number ordering, in contrast to a strong forward directional advantage in letter ordering. The speed of number access was found to steadily and evenly decrease along the numeric scale, in contrast to a systematic pattern of variations in alphabet access along the alphabetic scale. Finally, the middle item effect (the middle item in a multi-item array is identified most slowly) found in Jou's (1997) multiple-letter comparison study was generalized to numbers.

Babies get a kick out of serial memories

Science NewsVolume 154, Issue 4 p. 53-53 This Week Babies get a kick out of serial memories Bruce Bower, Bruce BowerSearch for more papers by this author Bruce Bower, Bruce BowerSearch for more papers by this author First published: 01 July 2009 https://doi.org/10.2307/4010670Citations: 1AboutPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinkedInRedditWechat No abstract is available for this article.Citing Literature Volume154, Issue4July 1998Pages 53-53 RelatedInformation

Development of high speed multichannel scalar using line memories

A high speed multichannel scaling mode time analyzer (MCS) for time of flight (TOF) experiments was developed by using high speed serial access memories and a personal computer. The MCS was composed of two memory banks, run alternately for each trigger. The channel width of the MCS was selected from 50 ns to 200 ns (4 stage). The count per channel per trigger signal was one, but the dead time for channel advancing may approach zero. The MCS was tested with linear accelerator (linac)-TOF experiments. The results agreed satisfactorily with the design goal. It was confirmed that the high speed MCS runs normally. A small discrepancy at high energy channels between the time spectrum of the MCS and that of the time-to-pulse-height converter (TPHC)-multichannel pulse height analyzer (PHA) time analyzer was observed. One of the reasons for the discrepancy was the uncertainty of the MCS start time after the trigger signal by linac because of asynchronous crystal oscillations with the linac trigger signal.

Multiprocessors with a serial multiport memory and a pseudo crossbar of serial links used s a processor-memeory switch

This paper presents an inventive information exchange pro-cess between the main memory and cache equipped processors. It makes use of serial multiport memories and high throughput serial transmission supports. It is then possible to consider the realization of a multiprocessor with a common memory shared by several hundreds processors set with a performance level close to that of a crossbar network one's without having its disadvantages. This exchange process generates a family of possible architectures in which serial transfers of informations are parallelized, in the contrary of conventional architectures which serialize parallel transfers of informations.

IEE Review. Semiconductor memories

The paper reviews the evolution of semiconductor memories from the early 1960s to the present day. It includes descriptions and comparisons of the principal types of memory presently available, followed by a survey of the main semiconductor technologies used in the fabrication of VLSI memories. Typical cell designs are first presented, starting with basic electrical designs and proceeding to show how these may be implemented as layouts for a practical chip. The fabrication steps required to realise such cells within a memory chip are described. The design and organisation of complete memories is then discussed; the design of the principal types of read-only memories, read/write memories, content-addressable memories and serial memories being included. The remainder of the paper deals with the important topic of specification and timing requirements of memories; followed by a general review of different types of semiconductor memory, both from the applications point of view and as a comparison of their principal characteristics with those using alternative fabrication technologies. Finally, there is brief projection of future developments. The paper is written throughout primarily from the technological rather than the applications viewpoint.

Parallel Sorting with Serial Memories

This correspondence examines the problem of sorting on a network of processors, where each processor consists of a single storage register and a small control unit capable of comparing two numbers and has a single serial memory attached to it. We show how to sort optimally on one- or two-dimensional arrays of p processors in time θ(n + (n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> )) and θ((n/√p) + (n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> )), respectively. Because of the implementational advantages of serial memories, we feel that our architecture will be attractive for several applications.

Novel dynamic merged load technology

Two new device concepts for dynamic ratioless inverter logic circuits are presented. Very high circuit density is achieved by replacing the traditional MOS dynamic load transistor with a novel load element which is merged with the switching transistor. Both device types can be implemented with a relatively standard double polysilicon CMOS process and are ideally suited for very low-power digital signal processors, serial memories and correlators, and digital image processors.

A Packet/Circuit Switch

We propose a switch, suitable for an integrated local communications network, that will support packet switching and circuit switching, with a wide range of bit rates. Key components are two serial memories; a multiplicity of access units, each capable of writing and reading uniformly formatted, addressed information; and a programmed controller. Circuit switching is achieved when the controller repeatedly allocates memory slots, following call setup. Data communications can proceed concurrently without setup, competing for unused slots. We give an example of a 10,000-telephone-line switch carrying a similar load of other traffic. The switch would delay voice by less than 5 ms and could be interfaced to the existing telephone system. We indicate a method of fault detection and isolation that will limit the impact of a failure on a serial memory to an arbitrarily small group of connected lines. We define an index for measuring failure impact and use it to derive most-favorable fault-isolating partitions.

Bipolar detection for cross-tie memories

A new method of cross-tie data bit detection which produces bipolar output signals (positive for "ones" and negative for "zeroes") is described. It eliminates the pedestal voltage and the need for a threshold to distinguish between "ones" and "zeroes", and reduces temperature stability requirements on memory elements and sensing circuits. The new method provides a more reliable detection function in memory systems compared to that of unipolar signal detection and is applicable to both serial access and random access crosstie memories. Bipolar signals are obtained by proper design of the magnetoresistive detector region of the film element and by applying a magnetic bias field alongs its hard axis during readout. Experimental data from both serial and random access memory devices and analysis of a theoretical model for the magnetization, bias field and sensing current relationships are presented.

Wafer-scale integration-a fault-tolerant procedure

Considers a new approach to full-slice technology in relation to existing procedures for achieving this goal. Under external control a chain of good chips is created to form a long serial memory from an array of identical chips on a full slice. Bad chips are automatically bypassed without requiring any pre- or post-programming of the metallization and without any prior knowledge of the distribution of faulty chips on the wafer. Computer simulations of chain formation are described which demonstrate the feasibility of creating such serial memories at practicable dice-yield levels. The proposed logic design is summarized and its verification by TTL simulation is noted. The inherent fault and failure tolerance of the design are discussed and the potential problem areas of short-circuit chips, double-level metallization, spiral branching, thermal dissipation, and noise/pattern sensitivity are described together with suggested solutions.

Minimizing Latency in CCD Memories

Serial memories built from charge-coupled devices (CCD's) offer an opportunity for minimizing latency times not available with the more conventional drum and disk (serial) memory units. Let r be the ratio of the maximum to the minimum clocking rates for the CCD memory. We show that in many practical situations the average latency can be reduced from 1/2 to 1/(1 + √r) of a revolution time if the optimal clocking strategy is used when the CCD is idle.

Solid-state serial memories. The role of bubbles and c.c.d.s.

Solid-state memories are rapidly becoming the dominant medium for information storage in digital systems. Their ascendance has been steady, almost slow, until recently. The situation has changed dramatically during the last few years because of technology and circuit advances offering substantial benefits to the user in terms of cost, versatility and performance.

Solid-state serial memories—The role of bubbles and c.c.d.s. : K. Baker. Electron. Power p. 647 (September 1978)

Solid-state serial memories—The role of bubbles and c.c.d.s. : K. Baker. Electron. Power p. 647 (September 1978)

Multichannel analog transient acquisition system

A 16-channel data acquisition system MATAS-16 capable of receiving data with a sampling frequency up to 40 MHz has been built to process the signals from measurements on the Texas Turbulent Torus experiment. To avoid the necessity of using a number of fast (and expensive) digitizers, the signals are first stored in serial analog memories. Subsequently, they are sequentially read out, digitized, and stored in digital memory. These data are then transmitted to the computer for analysis and are graphically displayed. Delayed trigger, post-trigger, pretrigger, and change of sampling frequency during the data acquisition are also provided.

Overview of CCD memory

This paper summarizes the status and potential of charge-coupled device (CCD) memories. Cost-performance tradeoffs for serial memories are reviewed, and the CCD chip organizations for slow and fast access systems are discussed. Comparisons are made between CCD and MOS random access memory (RAM) chips on the basis of cell area, support circuits, cell operation, and technology.

Overview of CCD memory

This paper summarizes the status and potential of charge-coupled device (CCD) memories. Cost-performance tradeoffs for serial memories are reviewed, and the CCD chip organizations for slow and fast access systems are discussed. Comparisons are made between CCD and MOS random access memory (RAM) chips on the basis of cell area, support circuits, cell operation, and technology.

Frequency synthesis via the discrete chirp and prime sequence ROM's

Surface-acoustic-wave (SAW) sampled-data filters can be utilized as serial access READ-ONLY memories to directly implement at carrier frequencies a coherent fast-frequency-hop synthesizer in the VHF and UHF ranges. An example of frequency synthesis using surface acoustic wave discrete chirp filters is shown. A frequency synthesis scheme using a SAW prime-sequence filter is described.

Radiation Effects in Charge Coupled Devices

Charge coupled devices (CCD s) exhibit a number of advantages (low cost, low power, high bit density) in their several applications (serial memories, imagers, digital filters); however, fairly elementary theoretical considerations indicate that they will be very vulnerable to permanent radiation damage, by both neutrons and ionizing radiation, and to transient upset by pulsed ionizing radiation. Although studies of permanent ionizing-radiation damage in CCD's have been reported, little information has been published concerning their overall nuclear radiation vulnerability. This paper presents a fairly comprehensive experimental study of radiation effects in a 256-cell surface-channel, CCD shift- register. A limited amount of similar work is also presented for a 128-cell surface-channel device and a 130 cell peristaltic CCD shift register. The radiation effects phenomena discussed herein, include transient-ionizing- radiation responses, permanent ionizing- radiation damage to transfer efficiency, charge-carrying capacity and input transfer gate bias, and neutron damage to storage time--determined from dark current and charge-up time measurements. (auth)

Preprocessors for Remote Supervisory Control Stations

A building-block approach to implementing remote supervisory control stations is described. By structuring the interface between functional blocks to be compatible with a mini-computer I/O bus, small hardwired remotes can be easily upgraded into programmable remotes. Several hardware/software tradeoffs are involved in the system design. By utilizing inexpensive MOS serial memories and limited processing in the individual functional blocks, a more powerful hardwired remote can be realized without reducing the flexibility of the larger programmable remote. This preprocessing also permits a small mini-computer to handle a remote with a large number of data points.