Serial Fault Simulation Research Articles

Development and Verification of Serial Fault Simulation for FPGA Designs using the Proposed RASP-FIT Tool

Fault simulation is the critical approach for many applications such as fault detection & diagnostics, test set quality measurement, generation of test vectors, circuit testability, and many others along with the help of fault injection technique. The fault simulation approach is divided into many types. The most straightforward approach among them is a serial fault simulation. In the simulation process, the circuit under test is faulted, and a faulty copy is achieved by either using a simulator command technique or instrumentation technique. A fault simulator must examine the behaviour of specified target fault in design and classified as detected or undetected by the applied test patterns. To modify the original code is a very challenging and time-consuming task. Therefore, the RASP-FIT tool is developed, which alters the fault-free FPGA design, which is under investigation, at the Verilog HDL code level. It produces the copies of faulty design along with the top design file for several fault simulation methods. Using this tool, a serial fault simulation environment can easily be created with no much effort. In this work, a serial fault simulation method is verified and validated using the RASP-FIT tool for an ISCAS’85 benchmark design as an example.

A Practical Approach to Single Event Transient Analysis for Highly Complex Design

Single Event Transients are considerably more difficult to model, simulate and analyze than the closely-related Single Event Upsets. The work environment may cause a myriad of distinctive transient pulses in various cell types that are used in widely different configurations. We present practical methods to help characterizing the standard cell library using dedicated tools and results from radiation testing. Furthermore, we analyze the SET propagation in logic networks using a standard (reference) serial fault simulation approach and an accelerated fault simulation technique, taking in account both logic and temporal considerations. The accelerated method provides similar results as the reference approach while offering a considerable increase in the simulation speed. However, the simulation approach may not be feasible for large (multi-million cells) designs that could benefit from static analysis methods. We benchmark the results of a static, probabilistic approach against the reference and accelerated methods. Finally, we discuss the integration of the SET analysis in a complete Soft Error Rate analysis flow.

Differential fault simulation for sequential circuits

A new fast fault simulation algorithm called differential fault simulation, DSIM, for synchronous sequential circuits is described. Unlike concurrent fault simulation, for every test vector, DSIM simulates the good machine and each faulty machine separately, one after another, rather than simultaneously simulating all machines. Therefore, DSIM dramatically reduces the memory requirement and the overhead in the memory management in concurrent fault simulation. Also, unlike serial fault simulation, DSIM simulates each machine by reprocessing its differences from the previously simulated machine. In this manner, DSIM is more efficient than serial fault simulation. Experiments have shown that DSIM runs 3 to 12 times faster than an existing concurrent fault simulator. In addition, owing to the simplicity of this algorithm, DSIM is very easy to implement and maintain. An implementation consists of only about 300 lines of “C” language statements added to the event-driven true-value simulator in an existing sequential circuit test generator program, STG3. Currently DSIM uses the zero-delay timing model. The addition of alternative delay models is under development.

Algorithms for an Advanced Fault Simulation System in MOTIS

In this paper, we will present algorithms developed for an advanced fault simulation system in the MOTIS simulation environment. In particular, the algorithm to perform fault modeling and collapsing is first reviewed. Efficient algorithms to perform fault simulation are discussed in terms of fault list manipulation and primitive evaluation. The simulator realizes a speed gain factor of 787 to 2088 over serial fault simulation. Special emphasis is on an innovative fast unit delay fault simulation algorithm that achieves an additional 33-39-percent improvement in speed and 20-28-percent improvement in memory usage.