Sequence Pair Representation Research Articles

Sequence-Pair-Based Flow-Layer Physical Design Algorithm for Continuous-Flow Microfluidic Biochips

To address the problem that the two phases of flow-level physical design, i.e., component placement and routing, are usually considered separately and their interaction is neglected, resulting in the degradation of design quality and biochip execution efficiency, an effective sequence-pair-based flow-level physical design algorithm for continuous-flow microfluidic biochips is proposed. Firstly, based on the sequence-pair representation method which can quickly enumerate and calculate the placement solution, the component placement solution is obtained by the discrete particle swarm optimization algorithm with higher solving efficiency to further improve the quality of the placement solution. Then, the Manhattan distance between component pairs is considered as the basis for routing order in the routing stage, and the routing is performed by the negotiation-based routing algorithm to effectively reduce the number of crossings in the flow channel. Finally, the interaction between placement and routing is considered, and the placement is adjusted according to the feedback information of routing, thus bridging the component placement and routing phases. The benchmark test set of actual biochemical application reaction and synthesis is adopted, and the flow-level physical design algorithm based on simulated annealing placement and negotiated routing is reproduced as the comparison algorithm for the experiment. The experimental results show that the proposed algorithm optimizes the number of flow path intersections by 74.94%, the chip area by 5.04%, and the total flow path length by 16.88%, resulting in a high-quality flow path physical design solution.

A Binary Particle Swarm Optimization for IC Floorplanning

Background: In the field of IC physical design, there is a big problem in the IC floorplanning to find the early feedback to estimate the area, wire length, delay, etc. before IC fabrication. Objective: In this paper, minimization of the area and total wire length on the IC has been done using Binary Particle Swarm Optimization with sequence pair representation. Methods: Optimization of the IC floorplan works in two phases. In the first phase, the floorplan is constructed by sequence pair representation without any overlapping of the modules on IC floorplan. In the second phase, Binary Particle Swarm Optimization algorithm explores the packing of all modules in floorplan to find better optimal performances i.e. area and wire length. Results: The results obtained were compared with the solutions derived from other meta-heuristic algorithms, the area is improved maximum up to 10% and the wire length was improved maximum up to 28%. Conclusion: The Experimental results on Microelectronic Center of North Carolina benchmark circuits show that Binary Particle Swarm Optimization algorithm gives better convergence for the area and wire length optimization than other algorithms.

Solving an integrated cell formation and group layout problem using a simulated annealing enhanced by linear programming

This paper proposes a new approach to integrating the cell formation, group layout of rectangle-shaped machines and routing selection problems. The problem is formulated as a mixed-integer program with the objective of minimizing the handling costs. Due to the computational complexity of the problem, a hybrid simulated annealing (SA) is employed to solve the problem. The sequence-pair representation, originally proposed for block placement, is utilized for solution encoding. Two placement algorithms are developed to evaluate the objective function value of an encoded solution in the SA. The first placement algorithm is based on solving a linear program embedded with a constraint reduction algorithm. The second one is a fast heuristic that can evaluate an encoded solution in much less computational time. Benchmarks selected from the literature are solved to verify the performance of the SA and to accomplish comparisons. The computational results demonstrated the high performance of both designed hybrid SA algorithms. The comparison against the literature also indicated that the flexibility incorporated into the model results in better layouts, even if the model is solved only by a solver such as CPLEX.

Solving a stochastic berth allocation problem using a hybrid sequence pair-based simulated annealing algorithm

ABSTRACTIn this article, a continuous berth allocation problem is studied with stochastic ship arrival and handling times. The objective is to minimize a weighted sum of the expected waiting costs, berthing deviation costs and expected overtime costs. The sequence pair representation is utilized to project the solution space of the problem into two permutations. Then, a scenario-based method is used to capture the uncertainty. To effectively solve the problem over the sequence pair solution space, a simulated annealing is combined with two algorithms. One of the algorithms is used to determine the berthing positions and the other one is used to determine the berthing times. Computational experiments are conducted to evaluate the performance of the solution method and to verify the advantages of the proposed stochastic approach. The results indicate that the proposed methodology is both efficient and effective.

Simultaneous optimization of layout and task schedule for robotic cellular manufacturing systems

Multi-robot cellular manufacturing systems utilize several articulated industrial robots that cooperatively perform a large number of complex operations when assembling products. To enhance the system performance when designing layouts for such robotic cellular manufacturing systems, the positions of robots and other manufacturing system components must be appropriately determined by considering the sequence of tasks the robots conduct during the assembly process. This paper proposes a new multiobjective layout design optimization technique for robotic cellular manufacturing system layouts that can simultaneously determine the positions of manufacturing components and also task scheduling. First, in this paper, sequence-pair representation is used to specify layout design candidates that inherently avoid interference between assembly system components, and the use of dummy components is introduced to represent layout areas that provide necessary and appropriate spacing between manufacturing system components. In addition, task allocations for each robot are considered as discrete design variables. The design criteria for robot cellular manufacturing system layout designs are clarified and the layout design problem is formulated as a multiobjective optimization problem. To solve the optimization problem, a method based on a multiobjective genetic algorithm is proposed and numerical examples are provided to demonstrate the effectiveness of the proposed method.

Handling precedence constraints in scheduling problems by the sequence pair representation

In this paper, we show that sequence pair (SP) representation, primarily applied to the rectangle packing problems appearing in the VLSI industry, can be a solution representation of precedence constrained scheduling. We present three interpretations of sequence pair, which differ in complexity of schedule evaluation and size of a corresponding solution space. For each interpretation we construct an incremental precedence constrained SP neighborhood evaluation algorithm, computing feasibility of each solution in the insert neighborhood in an amortized constant time per examined solution, and prove the connectivity property of the considered neighborhoods. To compare proposed interpretations of SP, we construct heuristic and metaheuristic algorithms for the multiprocessor job scheduling problem, and verify their efficiency in the numerical experiment.

An elitist strategy genetic algorithm using simulated annealing algorithm as local search for facility layout design

A well-planned arrangement of manufacturing departments on a two-dimensional planar region considerably increases the efficiency of its production systems, which is termed facility layout problem (FLP). Conventional layout design approach often designs intercell layout (determining exact location of each department on shop floor area) and flow path layout design of material handling system (MHS) step by step in a sequential manner. This results in suboptimal solutions for FLP. In this paper, an integrated approach is adopted to design the intercell layout and the flow path layout of MHS simultaneously. The quality of the final layout is evaluated by minimizing total material handling cost. Sequence pair (SP) representation is used for layout encoding. The translation from SP to layout is efficiently made by longest common subsequence (LCS) methodology. An elitist strategy genetic algorithm using simulated annealing (E-GASAA) as a local search mechanism is developed and tested with four test problem instances available in the literature. Elitist strategy is incorporated to enhance convergence characteristic of the proposed algorithm. It is found that the proposed E-GASAA is able to produce best solutions consistently for the test problem instance of different sizes within acceptable computational effort. In addition to that, we tried to reduce the computational load with the help of adopted LCS computation methodology and achieved a good improvement.

Fully Dynamic Evaluation of Sequence Pair

In the electronic design automation field, as well as in other areas, problem instances and solutions are often subject to discrete changes. The foundational significance of efficient updates of the criterion value after dynamic updates, instead of recomputing it from scratch each time, has attracted a lot of research. In this paper, motivated by the significance of the sequence pair (SP) representation for floorplanning, we develop a fully dynamic algorithm of SP evaluation, that efficiently updates a criterion value after insertions and deletions of SP elements and after modifications of element weights. Our result is based on a new data structure for the predecessor problem, which maintains the whole history of its dynamic modifications, and the path-compression technique from the union-find problem, which efficiently support predecessor queries. Numerical experiments showed that our algorithm exhibits linear-time behavior and considerably reduces the time of SP evaluation, compared to other approaches.

An elitist strategy genetic algorithm for integrated layout design

While designing the layout of any manufacturing organizations, the primary objective is to decide an optimal arrangement of their departments (machines or cells) in a two-dimensional shop floor (facility) satisfying desired objectives, which is termed facility layout problem (FLP). In traditional layout design philosophy, the inter-cell layout and flow path layout design of material handling system (MHS) was carried out step by step in a sequential manner. This results in sub-optimal solutions for FLP. In this paper, an integrated approach is adopted to design the inter-cell layout and the flow path layout of MHS simultaneously. The quality of the final layout is evaluated by minimizing the weighted sum of two distance-based cost objectives namely, (1) total material handling cost. (2) Distance-weighted cost of total closeness rating score. Sequence-pair (SP) representation is used for layout encoding. The translation from SP to layout is efficiently done by longest common subsequence methodology. Due to NP-hard nature of the proposed problem, an elitist strategy genetic algorithm (ESGA) is developed and tested with three test problem instances available in the literature. It is found that the proposed ESGA algorithm is able to produce the best solutions consistently, twice faster than the standard GA for the test problem instances.

Multi-objective voltage island floorplanning using sequence pair representation

In the nanometer era of VLSI design, high power consumption is considered to be a “show-stopper” for many applications. Voltage island design has emerged as a popular method for addressing this issue. This technique requires multiple supply voltages on the same chip with blocks assigned to different supply voltages. Implementation challenges force blocks with similar supply voltages to be placed contiguous to one another, thereby creating “islands”. Classical floorplanners assume a single supply voltage in the entire chip and thus require additional design steps to realize voltage islands. In this paper we present a new multi-objective floorplanning algorithm based on the sequence pair representation that can floorplan blocks in the form of islands. Given the possible supply voltage choices for each block, the floorplanner simultaneously attempts to reduce power and area of the chip. Our floorplanner integrates the tasks of assigning blocks to different supply voltages and the placing of the blocks in the chip. Compared to previous work, the proposed floorplanner on average reduces the area overhead of the chip by 13.5% with 34% runtime improvement. As power and area are jointly optimized, we also explore the trade-off between these cost functions. Experimental results show that equal weight to area and power cost function do not provide the best floorplan solution.

Applying Fuzzy Technologies to Equivalence Learning in Protein Classification

When sequencing a new genome, its function and structure are important concerns, and inferring methods are based on protein sequence similarity methods. However, sequence groups differ in their parameters such as the number of group members and intra- and inter-class variability. A method that performs well on one group may not perform well on another group. Thus, learning similarity in a supervised manner could provide a general framework to set a similarity function to a specific sequence class. Here we describe a novel method that learns a similarity function between proteins by using a binary classifier and pairs of equivalent sequences (belonging to the same class) as positive samples, and non- equivalent sequences (belonging to different classes) as negative training samples. For sequence pair representation, we propose to use advanced techniques from fuzzy theory, including a sigmoid-type function for normalization and the class of Dombi operators that provide a more robust method. Using some additional constraints, the learned function turns out to be a valid kernel or metric function, and we present a new way of learning it, along with a new parameter-weighting technique. Using a dataset of archeal, bacterial, and eukaryotic 3-phosphoglycerate-kinase sequences (3PGK) and clusters from COG, we evaluate this equivalence learning method from a protein classification point of view. A receiver operator characteristic (ROC) analysis shows that we get a much more robust and accurate methodology for protein classification when these techniques are applied together. (See online Supplementary Material at www.liebertonline.com).

New perspectives in VLSI design automation: deterministic packing by Sequence Pair

In the paper we consider a problem of packing rectangular blocks on a plane, which is known as Block Packing Problem (BPP). This problem is a central issue of the modern VLSI chips design methods. Basing on a new interpretation of the Sequence-Pair representation of the packing solution-space, which is based on Complementary Mirror Constraint Graphs (CMCG), we develop the efficient method of neighborhood exploration. This method might be able to improve the efficiency of other neighborhood-based search methods, such as simulated annealing or tabu search, as well as, to construct efficient heuristics. We illustrate application of the developed method by constructing a heuristic algorithm for solving BPP and comparing its efficiency and effectiveness to the algorithms commonly used so far.

Heuristic approaches for the two- and three-dimensional knapsack packing problem

The maximum profit two- or three-dimensional knapsack packing problem packs a maximum profit subset of some given rectangles or boxes into a larger rectangle or box of fixed dimensions. Items must be orthogonally packed, but no other restriction is imposed to the problem. We present a new iterative heuristic for the two-dimensional knapsack problem based on the sequence pair representation proposed by Murata et al. [VLSI module packing based on rectangle-packing by the sequence pair. IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems 1996;15:1518–24] using a semi-normalized packing algorithm by Pisinger [Denser packings obtained in O ( n log log n ) time. INFORMS Journal on Computing 2007;19:395–405]. Solutions are represented as a pair of sequences. In each iteration, the sequence pair is modified and transformed to a packing in order to evaluate the objective value. Simulated annealing is used to control the heuristic. A novel abstract representation of box placements, called sequence triple, is used with a similar technique for the three-dimensional knapsack problem. The heuristic is able to handle problem instances where rotation is allowed. Comprehensive computational experiments which compare the developed heuristics with previous approaches indicate very promising results for both two- and three-dimensional problems.

Multi-bend bus driven floorplanning

In this paper, the problem of bus-driven floorplanning is addressed. Given a set of blocks and bus specifications (the width of each bus and the blocks that the bus need to go through), we will generate a floorplan solution such that all the buses go through their blocks, with the area of the floorplan and the total area of the buses minimized. The approach proposed is based on a simulated annealing framework. Using the sequence pair representation, we derived and proved some necessary conditions for feasible buses, for which we allow 0-bend, one-bend, or two-bend. A checking will be performed to identify those buses that cannot be placed simultaneously. Finally, a solution will be generated giving the coordinates of the modules and the buses. Comparing with the results of the most updated work on this problem by Xiang et al. [Bus-driven floorplanning, in: Proceedings of IEEE International Conference on Computer-Aided Design, 2003, pp. 66–73], our algorithm can handle buses going through many blocks and the dead space of the floorplan obtained is also reduced. For example, if the buses have to go through more than 10 blocks, the approach in Xiang et al. [Bus-driven floorplanning, in: Proceedings of IEEE International Conference on Computer-Aided Design, 2003, pp. 66–73] is not able to generate any solution while our algorithm can still give solutions of good quality.

Denser Packings Obtained in O(n log log n) Time

The placement problem is that of packing a set of rectangles into a minimum-area enclosing rectangle. Since it is difficult to optimize directly on a placement, a number of topological representations have been presented in the literature. One of the most successful is the sequence pair representation. As opposed to previous papers using sequence pair, we do not make use of the corresponding constraint graph, but interpret the sequences as a packing order in a constructive algorithm. All placements generated are semi-normalized, i.e., each module is moved as far left and down as possible according to the current packing contour. It is shown that the two interpretations are equivalent for any minimum-area placement, and for a given sequence pair the new interpretation results in a placement using no more area than the constraint graph interpretation. The transformation runs in O(nlog log n) time and it is able to handle various constraints on the location of modules. Computational results based on a simulated-annealing framework show that the algorithm is able to improve significantly on the best found solutions for benchmark very large-scale integrated (VLSI) circuit design problems using less than ten seconds of CPU time. For large packing problems it is able to find solutions quickly that waste no more than 3%–5percnt; of the space.

A sequence-pair representation and MIP-model-based heuristic for the facility layout problem with rectangular departments

In Facility Layout Problem (FLP) research, the continuous-representation-based FLP can consider all feasible all-rectangular-department solutions. Given this flexibility, this representation has become the representation of choice in FLP research. Much of this research is based on a methodology of Mixed-Integer Programming (MIP) models. However, these MIP-FLP models can only solve problems with a limited number of departments to optimality due to the large number of combinations of the binary variables used in the models to maintain feasibility with respect to departments overlapping. Our research centers around the sequence-pair representation, a concept that originated in the Very Large Scale Integration (VLSI) design literature. We show that an exhaustive search of the sequence-pair solution space will result in finding the optimal layout of the MIP-FLP and that every sequence-pair solution is position consistent (although possibly not layout feasible) in the MIP-FLP. We propose a genetic-algorithm-based heuristic that combines the sequence-pair representation with the MIP-FLP model. Numerical experiments based on different sized test problems from both the literature and industrial applications are provided and the solutions are compared with both the optimal solutions and the solutions from other heuristics to show the effectiveness and efficiency of our heuristic. For 11 data sets from the literature we provide solutions better than those previously found. For two large industrial application data sets we perform a sensitivity analysis with respect to the department aspect ratio constraint.

Applying the sequence-pair representation to optimal facility layout designs

We present a new formulation for the facility layout problem based on the sequence-pair representation, which is used successfully in VLSI design. By tightening the structure of the problem with this formulation, we have extended the solvable solution space from problems with nine departments to problems with eleven departments.

Packing-based VLSI module placement using genetic algorithm with sequence-pair representation

The sequence-pair, a data structure with applications in packing-based VLSI module placement, has received significant amounts of research effort as the core of simulated annealing optimisers. Nevertheless, its application within genetic algorithm frameworks has not been adequately investigated. This paper presents a genetic algorithm approach to rectangle packing using the sequence-pair. The method is extended to handle symmetry constraints, a requirement often arising in the placement of analogue circuits. Genetic operators are developed taking into account the specific properties of the sequence-pair, and the algorithm is tested on several MCNC benchmarks.

Fixed-outline floorplanning: enabling hierarchical design

Classical floorplanning minimizes a linear combination of area and wirelength. When simulated annealing is used, e.g., with the sequence pair representation, the typical choice of moves is fairly straightforward. In this paper, we study the fixed-outline floorplan formulation that is more relevant to hierarchical design style and is justified for very large ASICs and SoCs. We empirically show that instances of the fixed-outline floorplan problem are significantly harder than related instances of classical floorplan problems. We suggest new objective functions to drive simulated annealing and new types of moves that better guide local search in the new context. Wirelength improvements and optimization of aspect ratios of soft blocks are explicitly addressed by these techniques. Our proposed moves are based on the notion of floorplan slack. The proposed slack computation can be implemented with all existing algorithms to evaluate sequence pairs, of which we use the simplest, yet semantically indistinguishable from the fastest reported . A similar slack computation is possible with many other floorplan representations. In all cases the computation time approximately doubles. Our empirical evaluation is based on a new floorplanner implementation Parquet-1 that can operate in both outline-free and fixed-outline modes. We use Parquet-1 to floorplan a design, with approximately 32000 cells, in 37 min using a top-down, hierarchical paradigm.

Floorplanning using a tree representation a summary

We present an ordered tree (O-tree) structure to represent nonslicing floorplans. The O-tree uses only n (2+[lg n]) bits for a floorplan of n rectangular blocks. We define an admissible placement as a compacted placement in both x and y directions. For each admissible placement, we can find an O-tree representation. We show that the number of possible O-tree combinations is O(n!2/sup 2n-2//n/sup 1.5/). This is very concise compared to a sequence pair representation that has O((n!) <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) combinations. The approximate ratio of sequence pair and O-tree combinations is O(n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (n/4e)/sup n/). The complexity of an O-tree is even smaller than a binary tree structure for a slicing floorplan that has O(n!2/sup 5n-3//n/sup 1.5/) combinations. Given an O-tree, it takes only linear time to construct the placement and its constraint graph. We have developed a deterministic floorplanning algorithm utilizing the structure of O-tree. Empirical results on MCNC (www.mcnc.org) benchmarks show promising performance with average 16% improvement in wire length and 1% less dead space over the previous central processing unit (CPU) intensive cluster refinement method.