Semiconductor Optical Amplifier Technology Research Articles

InP photonic integrated multi-layer neural networks: Architecture and performance analysis

We demonstrate the use of a wavelength converter, based on cross-gain modulation in a semiconductor optical amplifier (SOA), as a nonlinear function co-integrated within an all-optical neuron realized with SOA and wavelength-division multiplexing technology. We investigate the impact of fully monolithically integrated linear and nonlinear functions on the all-optical neuron output with respect to the number of synapses/neuron and data rate. Results suggest that the number of inputs can scale up to 64 while guaranteeing a large input power dynamic range of 36 dB with neglectable error introduction. We also investigate the performance of its nonlinear transfer function by tuning the total input power and data rate: The monolithically integrated neuron performs about 10% better in accuracy than the corresponding hybrid device for the same data rate. These all-optical neurons are then used to simulate a 64:64:10 two-layer photonic deep neural network for handwritten digit classification, which shows an 89.5% best-case accuracy at 10 GS/s. Moreover, we analyze the energy consumption for synaptic operation, considering the full end-to-end system, which includes the transceivers, the optical neural network, and the electrical control part. This investigation shows that when the number of synapses/neuron is >18, the energy per operation is <20 pJ (6 times higher than when considering only the optical engine). The computation speed of this two-layer all-optical neural network system is 47 TMAC/s, 2.5 times faster than state-of-the-art graphics processing units, while the energy efficiency is 12 pJ/MAC, 2 times better. This result underlines the importance of scaling photonic integrated neural networks on chip.

Lossless Photonic Integrated Add-Drop Switch Node for Metro-Access Networks

We assess the performance of a modular photonic integrated circuit (PIC) for space and time optical switching as an optical add-drop node for metro-access network applications. The PIC based on semiconductor optical amplifier (SOA) technology enables the implementation of compact, low cost and lossless add-dropping through fast optical switching. Data integrity measurements demonstrate error-free switching operation with less than 1 dB and 2.5 dB power penalty for 10 Gb/s and 40 Gb/s NRZ OOK optical signal, respectively. The dynamic control of the SOA based optical gates by the switch controller permits the power equalization of the switched channels. The experimental results also demonstrate dynamic forwarding, dropping and multicasting operation for a packetized 10 Gb/s NRZ OOK optical signal. The transparency of the SOA technology towards the optical signal’s data rate allows to avoid costly and power consuming dedicated interfaces at the add-drop node and open a path towards efficient statistical multiplexing.

Deep Neural Network Through an InP SOA-Based Photonic Integrated Cross-Connect

Photonic neuromorphic computing is raising a growing interest as it promises to provide massive parallelism and low power consumption. In this paper, we demonstrate for the first time a feed-forward neural network via an 8 × 8 Indium Phosphide cross-connect chip, where up to 8 on-chip weighted addition circuits are co-integrated, based on semiconductor optical amplifier technology. We perform the weight calibration per neuron, resulting in a normalized root mean square error smaller than 0.08 and a best case dynamic range of 27 dB. The 4 input to 1 output weighted addition operation is executed on-chip and is part of a neuron, whose non-linear function is implemented via software. A three feedback loop optimization procedure is demonstrated to enable an output neuron accuracy improvement of up to 55%. The exploitation of this technology as neural network is evaluated by implementing a trained 3-layer photonic deep neural network to solve the Iris flower classification problem. Prediction accuracy of 85.8% is achieved, with respect to the 95% accuracy obtained via a computer. A comprehensive analysis of the error evolution in our system reveals that the electrical/optical conversions dominate the error contribution, which suggests that an all optical approach is preferable for future neuromorphic computing hardware design.

Broadband lasers for photo-ionization and repumping of trapped ions

A frequency-stable, broadband laser is presented for experiments on trapped ions. Since the design is based on widely available semiconductor optical amplifier technology, similar lasers can be realized for virtually any wavelength in the near-infrared, and the coherence properties and output power allow for efficient second harmonic generation. No closed-loop frequency stabilization for addressing Doppler- or naturally-broadened, dipole-allowed transitions is needed, and the light source can be turned on and off during a measurement cycle with sub-microsecond response time. As a case study, a 921.7-nm laser with an output power of 20mW and a linewidth of 10GHz is realized, which is then frequency doubled to 460.9nm for excitation of strontium as the first step in photo-ionization. The excitation efficiency is compared to that achievable with a narrow-linewidth distributed Bragg reflector laser as well as to theory.

Programmable Adaptive BVT for Future Optical Metro Networks Adopting SOA-Based Switching Nodes

Adaptive Sliceable-Bandwidth Variable Transceivers (S-BVTs) are key enablers for future optical networks. In particular, those based on Discrete MultiTone (DMT) modulation and Direct Detection (DD) can be considered a flexible solution suitable to address the cost efficiency requirement of optical metro networks. In this paper, we propose to use a cost-effective S-BVT option/implementation in optical metro networks adopting switching nodes based on Semiconductor Optical Amplifier (SOA) technology. Bit loading (BL) and power loading (PL) algorithms are applied to the Digital Signal Processing (DSP) modules, to maximize the performance and/or the capacity as well as enhance the flexibility and adaptability of the system. Our analysis considers switching nodes based on SOAs with and without filtering elements and fiber spans of 25 km. We present the results up to 100 km, with and without SOA-based nodes. Firstly, we analyze the adaptive BVT transmission using the Margin Adaptive (MA) BL/PL algorithm at a fixed bit rate of 28 Gb/s. The possibility of controlling the SOAs current is a key factor to face the transmission impairments due to the fiber and the filtering elements. We also analyze the system considering Rate Adaptive (RA) transmission at a fixed target Bit Error Rate (BER) of 3.8 × 10−3, showing that a maximum capacity above 34 Gb/s can be achieved for a single span of 25 km. Although the cascading of filtering elements still constitutes a limiting factor, we show that an improvement of the net bit rate performance can be obtained thanks to the combined use of BVT and SOA technology at the switching nodes, resulting in a promising approach for designing future optical metro networks.

Evaluation of Power Consumption in Low Spatial Complexity Optical Switching Fabrics

In this paper, we propose an analytical model to evaluate the power consumption in the switching fabric of a bufferless shared-per-wavelength (SPW) optical packet switch architecture in which one bank of wavelength converters (WC) is dedicated to each wavelength. We assume that both optical gates and WCs are realized in semiconductor optical amplifier technology. In our evaluation, we account for the power consumption of the current drivers needed to both controlling the used active devices and supplying the thermoelectric coolers. SPW allows for a complexity reduction of the spatial switching matrix that leads to reduced power consumption with respect to other switching architectures. Results show the effectiveness in terms of consumed power of the considered architecture with respect to the shared-per-node reference architecture, where a fully sharing strategy of WCs is adopted. The main results show that SPW allows us to reduce the power consumption in the order of 26% for offered traffic equal to 0.6. The obtained results also show how the fabric switching of the SPW optical packet switch consumes much less power per gigabits per second carried than the one of a typical commercial core router.

Power Consumption in Bufferless Optical Packet Switches in SOA Technology

Increase in data transmission and processing speed unavoidably leads to high requirements on power supply. Especially in the case of high- capacity electronic routers, the question of power consumption will be the major issue and probably the most important limiting factor for the future. This paper analyzes the role of bufferless optical packet switches (OPSs) realized in semiconductor optical amplifier (SOA) technology in reducing average power consumption. An analytical model is proposed to provide an expression for the average power consumption of bufferless OPSs as a function of both the offered traffic and the main parameters characterizing the power consumption of the space switching modules (SSMs) and wavelength converters (WCs) needed to realize the bufferless OPSs. The effectiveness of WC sharing, which reduces the average power consumed by WCs, is evaluated in the case in which the Tucker's model for the evaluation of the power consumed by the SSMs and WCs is used. The obtained results show that, due to the high power consumed by the switching elements, switches with shared WCs may require average power consumption higher than switches in which WC sharing is not performed. In particular, only when the offered traffic is low and high-energy-consumption WCs are used, is the WCs sharing effective. When cross-gain modulation WCs are employed, the sharing technique allows for a reduction of average power consumption from 50% to 10% when the offered traffic is varying from 0.1 to 0.9. To obtain more realistic power consumption of the bufferless OPSs, we have introduced in our analytical model some power consumption values evaluated and experimentally validated for the SOAs produced by some manufacture's and needed to realize the SSMs and WCs. In this case we compare the power consumed of the bufferless OPSs to that of a Cisco GSR 12008 router equipped with ten slots that can accommodate up to 4 Gb/s per slot and designed for operation in a network core. We take into account for comparison the power consumption normalized to the offered total input bit rate.

Scalable optical switches for computing applications [Invited

A scalable photonic interconnection network architecture is proposed whereby a Clos network is populated with broadcast-and-select stages. This enables the efficient exploitation of an emerging class of photonic integrated switch fabric. A low distortion space switch technology based on recently demonstrated quantum-dot semiconductor optical amplifier technology, which can be operated uncooled, is used as the base switch element. The viability of these switches in cascaded networks is reviewed, and predictions are made through detailed physical layer simulation to explore the potential for larger-scale network connectivity. Optical signal degradation is estimated as a function of data capacity and network size. Power efficiency and physical layer complexity are addressed for high end-to-end bandwidth, nanosecond-reconfigurable switch fabrics, to highlight the potential for scaling to several tens of connections. The proposed architecture is envisaged to facilitate high-capacity, low-latency switching suited to computing systems, backplanes, and data networks. Broadband operation through wavelength division multiplexing is studied to identify practical interconnection networks scalable to 100 Gbits/s per path and a power consumption of the order of 20 mW/(Gbits/s) for a 64×64 size interconnection network.

Dynamic control analysis for semiconductor optical amplifier dynamics in optical network applications

For the first time a practical control analysis of semiconductor optical amplifier (SOA) dynamics has been conducted with implementation design considerations, based on a newly developed SOA electrical Spice model. It can be used for optimal design of SOA driver and control circuits within any existing optical network. In addition, a novel dual-control loop is designed and simulated. The two control loops overcome both fast (transient) and slow (steady-state) phenomena. Simulation results of the controlled SOA dynamics are presented, with an implementation example of an SOA high-speed optical switch driver. For optical switching the SOA driver uses a pre-impulse-step injected current as the switching signal. The developed Spice SOA electrical model is used for the predistortion optimization. The simulation results show that an ultrafast driver and control circuit seems feasible. It is also shown that the SOA can operate as a variable attenuator. A dynamic time constant of ~1–2 nsec is achievable using the predistortion scheme. The design and analysis here show that the SOA technology can be used as the switch-fabric core of a bufferless optical network with switching on packet timescales.