Semiconductor Industry Association Roadmap Research Articles

Insights on Design and Scalability of Thin-BOX FD/SOI CMOS

Device simulations are used to gain insights on the design of nanoscale thin-buried-oxide (and ultrathin-body) fully depleted/silicon-on-insulator (SOI) CMOS and to assess its scalability toward the end of the Semiconductor Industry Association roadmap (International Technology Roadmap for Semiconductors), relative to that of FinFET CMOS. The simulation results imply, albeit with complex processing, good scalability and performance for low-power (LP) applications (including static random access memory), defined by minimum viable SOI thickness. However, the scalability for high-performance (HP) applications is limited, but the processing can be simplified. Results for double-gate FinFETs are better, showing good scalability and performance to the end of the ITRS for both HP and LP applications.

Extreme ultraviolet lithography mask flatness and electrostatic chucking analysis

The Semiconductor Industry Association Roadmap for Extreme Ultraviolet Lithography (EUVL) calls for significant improvements in the quality and flatness of the substrate and patterned mask. Due to the difficulty of meeting the mask flatness specifications, an alternative strategy has been proposed to ensure that suitable substrates will be available for EUVL. A new SEMI standard for EUVL electrostatic chucks is currently being developed. If such a standard were established, then the flatness requirements for the substrate might be relaxed to permit certain types of bow that can later be flattened by the chuck. The purpose of this study is to identify which shapes can indeed be flattened by an electrostatic chuck. To support the proposed strategy, it is essential that the clamping ability of the electrostatic chuck be characterized and well-understood. The ability of the chuck to flatten the mask will depend primarily on the mechanical stiffness of the chuck and the clamping pressure. Legendre polynomials have been identified as an effective and efficient means of representing EUVL mask surface shapes. Finite element (FE) models have been developed to utilize the Legendre polynomials as input data to define the surfaces of the reticle. The FE models were then used to determine the clamping response of the various mask shapes. In particular, the maximum reticle-to-chuck gap within the flatness quality area and over the entire reticle has been tracked as a function of clamping pressure and chuck thickness for the low-order Legendre modes.

Electron holographic characterization of ultra-shallow junctions in si for nanoscale MOSFETs

This investigation attempts quantitative characterization of ultra-shallow junctions (USJs) in Si, useful for future generations of nanoscale MOSFETs as predicted by the Semiconductor Industry Association Roadmap. The USJs were fabricated using rapid thermal diffusion (RTD) from a heavily doped n-type surface source onto a heavily doped p-type substrate. The dopant profiles were analyzed using secondary ion mass spectrometry (SIMS), and were further used to calculate the metallurgical junction depth (MJD). One-dimensional (1-D) characterization of the electrical junction depth (EJD) associated with the electrically activated fraction of the incorporated dopants was performed using off-axis electron holography in a transmission electron microscope. 1-D potential profiles were derived from the unwrapped phase of the reconstructed holograms. The EJD was derived from the measured potential distribution across the p-n junction, and quantitative comparison is made with MJD derived from the SIMS profiles. The comparison between calculated electric field and total-charge distributions from the measured potential profiles and the simulated distributions using the SIMS profiles provides a quantitative estimate of the electrical activation of dopants incorporated by the RTD process, within the accuracy limits of this technique, which is discussed herein.

157nm Lithography. Window of Opportunity.

This keynote paper looks at the window of opportunity for 157nm lithography. The issues and challenges of the new 157nm lithography are identified and reviewed in the context of optical scanning system development. Major developments associated with the solution to problems are detailed: Optical material development; birefringence of optical materials; convergence of optics designs; contamination purging; and 157nm laser illumination. Micrascan VII and AT systems are highlighted.Resolution performance is projected against the Semiconductor Industry Association Roadmap. Both measured data as well as predictions of system performance are given. The window of opportunity for 157nm lithography is confirmed.

The Role of Nanoscale Silicon in Optical Interconnects

ABSTRACTThe semiconductor industry association roadmap has identified interconnects as a major barrier to progress starting in 2010. Optical interconnects (OI) offer an attractive solution for chip-to-chip communications, however there is no general agreement on how to design them. Eventually, OI may also perform a large amount of intra-chip clocking and signaling, which implies that any chip-to-chip OI system must be designed to be compatible with intra-chip OI, from the points of view of manufacturability, architecture, and device design. We are exploring the use of nanoscale silicon for OI. This paper reports progress toward the demonstration of two basic building blocks of an OI system, namely a Si laser and a Si-based modulator.

Status and review of two-dimensional carrier and dopant profiling using scanning probe microscopy

An overview of the existing two-dimensional carrier profiling tools using scanning probe microscopy includes several scanning tunneling microscopy modes, scanning capacitance microscopy, Kelvin probe microscopy, scanning spreading resistance microscopy, and dopant selective etching. The techniques are discussed and compared in terms of the sensitivity or concentration range which can be covered, the quantification possibility, and the final resolution, which is influenced by the intrinsic imaging resolution as well as by the response of the investigated property to concentration gradients and the sampling volume. From this comparison it is clear that, at present, none of the techniques fulfills all the requirements formulated by the 1997 Semiconductor Industry Association roadmap for semiconductors [National Technology Roadmap for Semiconductors (Semiconductor Industry Association, San Jose, CA, 1997)]. Most methods are limited to pn-junction delineation or provide a semiquantitative image of the differently doped regions. However, recent comparisons have shown that the techniques can provide useful information, which is not accessible with any other method.

Lithography for sub-60 nm resist nanostructures

As the semiconductor community continues to follow the Semiconductor Industry Association Roadmap, resist structures are being printed further into the nanometer domain. However, a persistent issue for successful sub-60 nm resist patterning is mechanical stability at high aspect ratios. The objective of this article is to understand what processing conditions facilitate processing resist nanostructures with useful aspect ratios for the fabrication of sub-60 nm transistors. We have found that, in aqueous based development and rinse, if the resist thickness is reduced, then the aspect ratio is sacrificed for the sake of resolution. The implication is that there is a resolution limit at which resist structures will have aspect ratios that are useful for device fabrication. We have also found that there are development effects that occur in the thick film regime that are not reproducible with thin films. The best resolution structures we have been able to print are lines of 28 nm in width using direct write electron-beam lithography on negative chemically amplified resists NEB-22 and NEB-31 (Sumitomo Chemical Inc.) with an aspect ratio of about 3. To put this result in perspective, this is about 40 molecules wide.

Specular electron scattering in metallic thin films

Specular electron scattering at the surface of metallic thin films is an important phenomenon for a class of magnetic multilayers known as giant magnetoresistance (GMR) spin valves. In the very best GMR spin valves, a significant part of the GMR effect is attributable to specular electron scattering. We have investigated the importance of specular electron scattering by developing surface-modification techniques that produce diffuse electron scattering. We have used these techniques to investigate specular electron scattering in GMR spin valves and in pure metals. Some of the largest effects are found in Au films. It is noted that specular electron scattering will be a highly desirable property in future generations of microelectronic interconnects as the feature size approaches the mean free path of the conduction electrons. In order to meet the Semiconductor Industry Association Roadmap requirements for interconnect resistivity, interconnects with highly specular surfaces must be developed.

Developments in equipment support technology

This article will review the achievements, on-going development activities and needs in “equipment support technology,” i.e., the critical or key components which surround the process chamber and without which an effective process cannot be reliably and repeatably executed. The challenges of the SIA (Semiconductor Industry Association) Roadmap have been the focus for the dramatic developments in many areas, such as the following: delivery of process material vapors into the reactor, control of the exhaust effluent from the reactor, on-process pressure measurement and control sensors and actuators, implementation of a well supported digital sensor bus introduced on 300 mm tool sets, tool and process diagnostics through residual gas analysis, and the incorporation of fault detection schemes and the eventual implementation of model based process control techniques. With the escalating cost of wafers-in-process, and the desire to increase overall equipment effectiveness and reduce cost-of-ownership, it becomes increasingly important to separate, control, diagnose and predict the behavior of critical process variables in real time. In-situ measurement, control, and metrology result in dramatically improved meantime between failures, shorter meantime to repair, and a significantly reduced cost per measurement function.

Potentials and challenges for lithography beyond 193 nm optics

The growth of the semiconductor industry continues to be driven to a large extent by steady advances in microlithography. Renewal of the Semiconductor Industry Association Roadmap is underway and accelerating requirements are predicted. The 130 nm generation is anticipated to be available in the year 2003, but the path to get there is not obvious. To meet the needs of its members, SEMATECH is embarking on a program to explore and narrow the technology options on the roadmap. The goal is to make a data-driven decision by late 1997. As an introduction to this Special Session on 0.13 Micron Lithography for Manufacturing, this article reviews the Lithography Technology Working Group requirements and potential solutions for roadmaps. The SEMATECH program to narrow the options beyond 193 nm optics is presented in detail, including the critical issues for each technology.

Photocatalytic oxidation for point-of-use abatement of volatile organic compounds in microelectronics manufacturing

In gas–solid heterogeneous photocatalytic oxidation (PCO), volatile organic compounds (VOCs) present in process air or air vents can be rapidly and completely oxidized to innocuous by-products over a near-ultraviolet (UV) illuminated titanium dioxide thin film catalyst at room temperature. This class of advanced oxidation processes appears to be well-suited for point-of-use VOC abatement in the microelectronics manufacturing industry. In this article, we review industrial requirements and unresolved technical issues in the context of the recently published Semiconductor Industry Association roadmap. The specific requirements for VOC abatement from a typical photolithography track are presented. Bench-scale PCO kinetics for target VOCs are reviewed to demonstrate the typical process behavior expected.