Semiconductor Design Research Articles

Selective Patterning of p‐Type Dopants on MoS2 via Atomic Force Microscopy‐Assisted Surface Modification

The selective patterning of gold chloride (AuCl3) dopants on few‐layer molybdenum disulfide (MoS2) flakes is investigated with the objective of manipulating the electrical properties of 2D material‐based devices. MoS2, renowned for its exceptional properties, is doped with AuCl3 via spin coating. The removal of the dopants is achieved using contact‐mode atomic force microscopy (AFM), with control over the extent of dopant obtained by varying the AFM tip's contact force. Scanning electron microscopy and energy‐dispersive X‐ray spectroscopy confirm the patterning of the dopants. The application of this patterning method to MoS2‐based field‐effect transistors results in rectified output characteristics, in contrast to the ohmic behavior observed in pristine and fully coated devices. This method offers a valuable approach for customizing MoS2 surfaces, advancing 2D material‐based electronic devices and next‐generation semiconductor designs with tailored properties.

Arbitrary Waveform Voltage Measuring Converter for Wideband AC Voltmeter

Alternating current (AС) voltage measurement is one of the most common types of measurements in various fields of science and technology. To evaluate the AC voltage level, special voltmeters are used which allow recording of amplitude, average and/or root mean square (RMS) voltage values. Among these measuring instruments, voltmeters of mean square voltage are especially significant because RMS is a fundamental physical characteristic of an electrical signal and is a true measure of power. The wide distribution of non-sinusoidal signals necessitates the creation of voltmeters for direct measurement of RMS. The main component of such voltmeter is an AC voltage to direct current (DC) voltage measuring converter based on the root-mean-square value level (AC RMS-DC converter). An analysis of existing technical solutions shows that it is advisable to use a thermoelectric converter (TEC) for high-precision measurement of RMS voltage of an arbitrary shape with a spectrum in the frequency band from 20 Hz to 20–50 MHz. Such a AC RMS-DC converter must contain a differential semiconductor TEC and an input broadband voltage amplifier with low nonlinearity of the frequency response. The aim of the paper was to develop a measuring AC RMS-DC converter of arbitrary shape voltage in which special attention is paid to modernization of the TEC and reduction of the AC RMS-DC converter error using corection of the frequency response of the input amplifier and introduction automatic calibration of the output voltage. Features of semiconductor chips and design of TEC in the form of a microcircuit or microassembly, results of converter’s and TEC elements’ parameters measurements are presented. A significant influence of the frequency response of the input amplifier and the offset voltage of the TEC transistors on the AC RMS-DC converter error was noted. Modernization of the input amplifier and introduction of automatic calibration of the output voltage ensured an error in a sinusoidal signal converting of less than 1 % in the range from 20 Hz to 50 MHz.

Graphene quantum dot modified Bi2MoO6 nanoflower for efficient degradation of BPA under visible light

Graphene quantum dots (GQDs) are a novel type of carbon dot material that has significant application value in the field of catalysis due to their non-toxic, stable, abundant surface functional groups, and quantum confinement effects. A unique composite photocatalyst was constructed by modifying GQDs onto Bi2MoO6 (BMO) microsphere-shaped nano petals using simple hydrothermal and sintering techniques. The structural and morphological characterization results indicate that GQDs with size of 10 ​nm are well dispersed on BMO nanosheets, forming close contacts, which can greatly improve the separation efficiency of photo-generated electron-hole pairs under visible light irradiation. In the evaluation of the catalytic performance of BPA solution (20 ​mg/L) with a catalyst content of 20 ​mg under a simulated light source with a power of 300 ​W, the best degradation performance was achieved by a photocatalyst (G6/BMO) with the GQDs mass ratio of 6 ​%, which degraded over 95 ​% of BPA under visible light within 120 ​min, while pure BMO only degraded about 45 ​% of BPA during the same time period. Even if the 400 ​nm filter is removed and directly exposed to Xe lamp radiation, the degradation performance of the optimal composite catalyst is only slightly improved, indicating that the current GQDs/BMO composite catalyst has extremely strong visible light catalytic activity. The improvement of catalytic performance comes from the effective separation of electron-hole pairs caused by the absorption of electrons by GQDs, and the introduction of GQDs to reduce the band gap and enhance visible light absorption, both of which are beneficial for catalytic reactions. Free radical capture and electron spin resonance (ESR) tests indicate that ·OH and ·O2− are the main active species for BPA degradation. Although the current GQDs/BMO catalysts have a simple structure, their catalytic performance has significantly improved, which will guide the design of other semiconductor based photocatalysts.

Multi-objective optimization and inverse design of complementary field-effect transistor using combined approach of machine learning and non-dominated sorting genetic algorithms for next-generation semiconductor devices

Complementary field-effect transistors (CFETs), which are structures in which different types of transistors are vertically stacked with a shared control gate, are being focused on for continuing to satisfy Moore's law by overcoming the limitations in pitch scaling. The structures of semiconductor devices become more complex as technology node shrinks, and interrelated multivariate parameters increase. In addition, predicting problems and proposing solutions by identifying complex patterns within extensive data collected for emerging semiconductor designs pose significant computational challenges and are inherently difficult. As a breakthrough in design technology co-optimization for advanced devices, this study developed a novel optimization framework integrating technology computer-aided design simulations, machine learning, and non-dominated sorting genetic algorithms. The developed framework provides unbiased optimal solutions, even in a high-dimensional objective space, while considering the tradeoff relationships between multiple variables. In addition, it enables inverse design to identify the design parameters of devices that satisfy specific electrical performance criteria using only a forward model, while achieving an error rate of less than 2%. Using this framework, we analyzed the operational mechanism of CFETs by comparing the inverse designs of various devices. This novel approach is particularly important when the design space is complex and extensive and is well suited for developing devices that emerge with technological advancements in the semiconductor industry.

In Situ Transmission Electron Microscope Observation of Ruthenium Silicadation and Diffusion Behavior at Atomic Scale

Ruthenium (Ru) has the excellent characteristics of oxidation resistance and good chemical stability; therefore, it has been widely used in semiconductor manufacturing, specifically in application as capping layers of extreme ultraviolet lithography (EUV) masks. The main purpose of capping layers is to protect Mo/Si multilayers from EUV radiation, preventing oxidation, damages, and contamination of the multilayers. However, with prolonged use, the EUV mask accumulates heat, resulting in diffusion between Ru and Si. When diffusion reactions occurred, leading to a reduction in the EUV mask's lifetime. In order to study the reaction mechanism, we use in-situ transmission electron microscopy (TEM) to observe the reactions between Ru and Si. In this study, Ru thin film was deposited on silicon substrate by electron gun (E-gun) evaporation. The dynamic formation process of ruthenium silicide has been observed via in-situ TEM. During the heating process, Si atoms diffused into ruthenium thin film at 300 °C, at the same time, Ru atoms will also diffuse into silicon substrate. At 350 °C, due to the interdiffusion effect, Ru2Si is formed in the Ru thin film, and it is observed that Ru2Si3 is embedded in the Si substrate. As the temperature rises to 450 °C, Ru2Si was transformed into RuSi. Finally, at 600 °C, the Ru thin film completely transformed into Ru2Si3. We provide direct evidence of diffusion behaviors and formation mechanism of Ru-Si system for better investigation of EUV masks degradation processes in semiconductor manufacturing and design. Keywords: Ruthenium silicide, in situ TEM, diffusion mechanism, atomic-scale, EUV mask Figure 1. Structural identification of Ru thin film and in-situ heating process of ruthenium silicide formation. (a) Initial EDS mapping of as-deposited Ru thin film on silicon substrate, showing homogenous distribution of each elements. (b) HRTEM image of in-situ heating process during 350oC. (c) Magnified HRTEM image of Ru2Si indicated in blue frame in (b). (d) Corresponding fast Fourier transform (FFT) along [110] zone axis. (e) HRTEM image of in-situ heating process during 600oC. (f) Magnified HRTEM image of Ru2Si3 indicated in yellow frame in (e). (g) Corresponding FFT along [010] zone axis. Figure 1

Special Issue on Semiconductor Design for Manufacturing (DFM)Joint Call for Papers

Special Issue on Semiconductor Design for Manufacturing (DFM)Joint Call for Papers

Special Issue on Semiconductor Design for Manufacturing (DFM)Joint Call for Papers

Special Issue on Semiconductor Design for Manufacturing (DFM)Joint Call for Papers

Correlation of quantum well periods on the 3rd order nonlinear optical responses of InGaN/GaN heterostructures

Semiconductor multi quantum well (MQW) design allows for the compression of electron-interaction dimensions, offering advantages for various applications, particularly in nonlinear optics. Despite the potential improvements in nonlinear optical responses, the influence of quantum well periods remains unexplored. In this study, we report the correlation of quantum well periods on the 3rd order nonlinear optical properties in In0.15 Ga0.85 N/GaN MQW using z-scan technique under femtosecond and continous wave laser regime. In0.15 Ga0.85 N well/GaN barrier with x1, x5, x10, x15 periods were grown by MOCVD technique. Good structural quality of grown MQWs were confirmed via HRTEM imaging, EDS, AFM and XRD. Absorption coefficient from UV-Vis coupled with PL emission spectrum shows systematic response of optical linear properties which provide an insight on the overall band gap structure. Positive nonlinear refraction, n2 and nonlinear absoprtion, β trends is observed under femtosecond an CW laser albeit differences of one order magnitude in χ3 value. The increase in χ3 value is shown to be monotonous with the increasing number of quantum well suggesting that compounding effect took place. This findings indicate the possibility of manipulating and tuning nonlinear reponses of MQW structures leading to improvement in semiconductor design in various areas such as optoelectronics, photonics, solar cell research, as well as quantum information processing.

Special Issue on Semiconductor Design for Manufacturing (DFM)Joint Call for Papers

Special Issue on Semiconductor Design for Manufacturing (DFM)Joint Call for Papers

Ultra-low-power CMOS ring oscillator with minimum power consumption of 2.9 pW using low-voltage biasing technique

Abstract The need for low-power low-voltage circuit so lutions increases significantly with the rapid spread of wireless sensor network (WSN) and energy harvesting applications. The design of Complementary Metal-Oxide Semiconductor (CMOS) oscillators in sub-threshold region is challenged by the limits of the minimum start-up sup ply voltage, the power available from the harvester, die area, the demand of fully integrated CMOS circuits, and the additional auxiliary circuits that are needed to stabilize the frequency vs a supply voltage V DD. In this work, low-power CMOS oscillator with a simplified design is proposed in order to overcome the aforementioned obstacles. The circuit is designed using 2.5 µm 2-polySi 2-metal CMOS technology from IMB–CNM (CSIC) [1] with a threshold voltage of n-channel metal oxide semiconductor NMOS and p-channel metal oxide semiconductor PMOS transistors of 0.86 and −1.52 V, respectively. The suggested oscillator is capable to start up even in the deep sub-threshold region at V DD of 0.25 V. Accordingly, the minimum power consumption is 2.9 pW with an oscillation frequency of 2 Hz. The circuit can produce a P–P voltage of the oscillation signal equal to the supply voltage within a power supply range of 0.25–1.25 V.

A Study on the Design Method of Hybrid MOSFET-CNTFET Based SRAM – A Secondary Publication

More than 10,000 carbon nanotube field-effect transistors (CNTFETs) have been successfully integratedinto one semiconductor chip using conventional semiconductor design procedures and manufacturing processes. Thesetransistors offer advantages such as high carrier mobility, large saturation velocity, low intrinsic capacitance, flexibility, andtransparency. The three-dimensional multilayer structure of the CNTFET semiconductor chip, along with ongoing researchin CNTFET manufacturing processes, increases the potential for creating a hybrid MOSFET-CNTFET semiconductorchip. This chip combines conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) and CNTFETs inone integrated system. This paper discusses a methodology to design 6T binary static random-access memory (SRAM)using a hybrid MOSFET-CNTFET. This paper introduces a method for designing a hybrid MOSFET-CNTFET SRAMby leveraging existing MOSFET SRAM or CNTFET SRAM design approaches. Additionally, this paper compares itsperformance with conventional MOSFET SRAM and CNTFET SRAM designs.

Joint Call for Papers for IEEE Transactions on Semiconductor Manufacturing and IEEE Transactions on Electron Devices: Special Issue on Semiconductor Design for Manufacturing (DFM)

Joint Call for Papers for IEEE Transactions on Semiconductor Manufacturing and IEEE Transactions on Electron Devices: Special Issue on Semiconductor Design for Manufacturing (DFM)

Special Issue on Semiconductor Design for Manufacturing (DFM)Joint Call for Papers

Special Issue on Semiconductor Design for Manufacturing (DFM)Joint Call for Papers

Special Issue on Semiconductor Design for Manufacturing (DFM)Joint Call for Papers

Special Issue on Semiconductor Design for Manufacturing (DFM)Joint Call for Papers

A Dual-Mode CMOS Power Amplifier with an External Power Amplifier Driver Using 40 nm CMOS for Narrowband Internet-of-Things Applications

The narrowband Internet-of-Things (NB-IoT) has been developed to provide low-power, wide-area IoT applications. The efficiency of a power amplifier (PA) in a transmitter is crucial for a longer battery lifetime, satisfying the requirements for output power and linearity. In addition, the design of an internal complementary metal-oxide semiconductor (CMOS) PA is typically required when considering commercial applications to include the operation of an optional external PA. This paper presents a dual-mode CMOS PA with an external PA driver for NB-IoT applications. The proposed PA supports an external PA mode without degrading the performances of output power, linearity, and stability. In the operation of an external PA mode, the PA provides a sufficient gain to drive an external PA. A parallel-combined transistor method is adopted for a dual-mode operation and a third-order intermodulation distortion (IMD3) cancellation. The proposed CMOS PA with an external PA driver was implemented using 40 nm-CMOS technology. The PA achieves a gain of 20.4 dB, a saturated output power of 28.8 dBm, and a power-added efficiency (PAE) of 57.8% in high-power (HP) mode at 920 MHz. With an NB-IoT signal (200 kHz π/4-differential quadrature phase shift keying (DQPSK)), the proposed PA achieves 24.2 dBm output power (Pout) with a 31.0% PAE, while satisfying −45 dBc adjacent channel leakage ratio (ACLR). More than 80% of the current consumption at 12 dBm Pout could be saved compared to that in HP mode when the proposed PA operates in low-power (LP) mode. The implemented dual-mode CMOS PA provides high linear output power with high efficiency, while supporting an external PA mode. The proposed PA is a good candidate for NB-IoT applications.

Fractional order capacitance behavior due to hysteresis effect of ferroelectric material on GaN HEMT devices

AbstractIn recent years, gallium nitride (GaN) high electron mobility transistors (HEMTs) have come to the forefront of the semiconductor industry because of their exceptional performance in both high‐power and high‐frequency utility. Accurate capacitance modeling is crucial to optimize performance and facilitate energy‐efficient electronic circuit design. In order to reflect the complex nature of the aluminum scandium nitride (AlScN) gate capacitance in GaN HEMTs this study investigates the use of the unique Grünwald‐Letnikov model based on fractional order calculus. The proposed model presents a powerful approach to accurately characterize capacitance since fractional order derivatives allow modeling of non‐integer order systems. Quantitative assessment of the Grünwald‐Letnikov model's accuracy is performed through various error metrics, including mean absolute error (MAE), root mean square error (RMSE), maximum percentage error (MPE), mean absolute percentage error (MAPE), and mean squared error (MSE), by comparing the model's predictions to experimental data. Notably, this model demonstrates remarkable consistency in error metrics, with maximum values of MPE = 0.21%, MAE = 0.05%, MAPE = 0.33%, MSE = 0.01%, and RMSE = 0.09% for the forward scan, and MPE = 0.32%, MAE = 0.04%, MAPE = 0.39%, MSE = 0.01%, and RMSE = 0.08% for the backward scan. These metrics affirm the model's precision in capturing the nuanced capacitance characteristics of GaN HEMT devices. Hence, herein for the first time, the novel Grünwald‐Letnikov model, augmented by fractional order calculus, proves to be a robust tool for accurately characterizing GaN HEMT capacitance. Its ability to seamlessly account for the complexities introduced by using ferroelectric material highlights its potential for advancing semiconductor design and optimizing device performance.

Chiplet Technology: Revolutionizing Semiconductor Design- A Review

This article explores the transformative journey of semiconductor design from monolithic structures to the cutting-edge era of chiplets. Chiplets, modular components offering specific functionalities, have emerged as a catalyst, reshaping the global semiconductor industry. Their capacity for tight interconnectivity, diverse applications, and cost-effective manufacturing marks a paradigm shift. The article delves into the historical context of Moore's Law, the rise of chiplets, and their impact on the semiconductor landscape. It further discusses key considerations in chiplet architecture, optimization algorithms, and future adoption in industries like data centers, mobile devices, AI, and automotive. Chiplet-based designs promise enhanced efficiency, collaboration, and innovation, heralding a new era in semiconductor evolution.

Cohesive Properties of Bimaterial Interfaces in Semiconductors: Experimental Study and Numerical Simulation Using an Inverse Cohesive Contact Approach.

Examining crack propagation at the interface of bimaterial components under various conditions is essential for improving the reliability of semiconductor designs. However, the fracture behavior of bimaterial interfaces has been relatively underexplored in the literature, particularly in terms of numerical predictions. Numerical simulations offer vital insights into the evolution of interfacial damage and stress distribution in wafers, showcasing their dependence on material properties. The lack of knowledge about specific interfaces poses a significant obstacle to the development of new products and necessitates active remediation for further progress. The objective of this paper is twofold: firstly, to experimentally investigate the behavior of bimaterial interfaces commonly found in semiconductors under quasi-static loading conditions, and secondly, to determine their respective interfacial cohesive properties using an inverse cohesive zone modeling approach. For this purpose, double cantilever beam specimens were manufactured that allow Mode I static fracture analysis of the interfaces. A compliance-based method was used to obtain the crack size during the tests and the Mode I energy release rate (GIc). Experimental results were utilized to simulate the behavior of different interfaces under specific test conditions in Abaqus. The simulation aimed to extract the interfacial cohesive contact properties of the studied bimaterial interfaces. These properties enable designers to predict the strength of the interfaces, particularly under Mode I loading conditions. To this extent, the cohesive zone modeling (CZM) assisted in defining the behavior of the damage propagation through the bimaterial interfaces. As a result, for the silicon-epoxy molding compound (EMC) interface, the results for maximum strength and GIc are, respectively, 26 MPa and 0.05 N/mm. The second interface tested consisted of polyimide and silicon oxide between the silicon and EMC layers, and the results obtained are 21.5 MPa for the maximum tensile strength and 0.02 N/mm for GIc. This study's findings aid in predicting and mitigating failure modes in the studied chip packaging. The insights offer directions for future research, focusing on enhancing material properties and exploring the impact of manufacturing parameters and temperature conditions on delamination in multilayer semiconductors.

Preparation and Application of Novel Power Semiconductor Chips

This study aims to improve the triggering current and dynamic characteristics of thyristor chips by designing new gate structures and multilayer semiconductor structures. Thyristor chips are essential components in power electronic devices, widely used in fields such as power transmission, motor control, and energy conversion systems. Trigger current is a key factor in the performance of thyristor chips, which is responsible for initiating the conduction state of the thyristor and carrying high current under high voltage conditions. This study improved the triggering current and dynamic characteristics of thyristor chips by optimizing the chip structure, especially by introducing multilayer P/N semiconductor design and improving the gate structure. The research results provide important guidance for the future development of thyristor chips and also contribute to the advancement of semiconductor technology.

Special Issue on Semiconductor Design for Manufacturing (DFM)Joint Call for Papers

Special Issue on Semiconductor Design for Manufacturing (DFM)Joint Call for Papers