SEMI Advanced Semiconductor Manufacturing Conference Research Articles

Guest Editorial Special section on the 2023 SEMI Advanced Semiconductor Manufacturing Conference

Guest Editorial Special section on the 2023 SEMI Advanced Semiconductor Manufacturing Conference

Guest Editorial Special Section on the 2022 SEMI Advanced Semiconductor Manufacturing Conference

Guest Editorial Special Section on the 2022 SEMI Advanced Semiconductor Manufacturing Conference

Guest Editorial Special Section on the 2019 SEMI Advanced Semiconductor Manufacturing Conference

Dear readers—We hope this editorial finds you and your family safe as we and the world battle—or, hopefully at the time of this publication, recover from—perhaps the greatest world-wide health crisis in the last century, COVID-19. Fortunately, the contributions of our semiconductor manufacturing industry over the last 40 years have put us in a much more comfortable position than those who faced past pandemics. It is likely that many of you have been working from home using your high-speed Internet connection and one of multiple computers that you and most families own. The worldwide Internet and computing infrastructure that our industry has enabled allows many engineers and others to VPN into work, communicate and share documents via e-mail, and attend video meetings. On the personal side, you can keep up with family and friends, with the latest news, and information and instructions from the government. Semiconductors allow your children to attend (or perhaps teach) school remotely. Certainly school aged children will be missing contact with their friends, but, fortunately, they can still video chat, message, or at least call friends with their mobile phones. The whole family can enjoy their favorite shows and movies via streaming services, and of course try new video games.

Study on Influence of O2 Concentration in Wafer Cleaning Ambient for Smoothness of Silicon (110) Surface Appearing at Sidewall of Three-Dimensional Transistors

The Si(110) surface appears at the sidewall of 3D transistors such as FinFET [1,2]. The surface micro-roughness of Si(110) strongly affects to the device characteristics because the Si(110) sidewall surface have a higher proportion of channel region width the miniaturization of width of fin structure [1,2]. In this work, we investigated the ambient in the wafer cleaning process to keep the smoothness of Si(110) surface.The wafers used in this study were Cz p-type Si(110) substrates having nearly 10 Ωcm. The wet oxidation of these substrates was performed at 1000 °C to form 300nm-thick silicon oxide films. Just after this oxide films were removed by HF solution, the average surface microroughness (Ra) of Si(110) measured by atomic force microscopy (AFM) was about 0.073 nm. We evaluated the influence of O2 concentration during the immersion in ultra pure water (UPW) by using N2 sealed glove box. The N2 sealed glove box can be controlled O2 concentration from 20% to 30 ppm. After the removing the chemical oxide with a diluted HF (0.5wt %) solution in this glove box with O2 concentration of 100 ppm, the wafers were immersed in UPW. We also evaluated for SOI wafer (20nm-thick Si(110) layer / 400nm-thick BOX layer / 725μm-thick Si(110) substrate) in a similar way.Figure 1 shows AFM images of Si(110) surface (a) before and after immersion in UPW for 24 hour in (b) 20% O2 (atmosphere) and (c) N2 ambient with O2 concertation less than 100ppm by using glove box. Ra drastically increase in the case of 20% O2 concentration. On the other hand, the increase of Ra is suppressed in N2 ambient with O2 concertation less than 100ppm. This indicates that the controlling of O2 concertation of ambient during the immersion in UPW is very effective to suppress the increase of Ra of Si(110) surface. It has been reported that the increase of Ra is caused by Si dissolving in UPW and Si dissolving in UPW is caused by the local oxidation just on Si surface [3,4].Figure 2 shows AFM images of Si(110) surface after immersion in UPW for 1, 3 and 24 hour in N2 ambient with O2 concertation of 100ppm. During the immersion in UPW, the O2 concentration was held 100 ppm. Figure 3 shows Ra as a function of immersion time for Si(110) surface in N2 ambient with O2 concertation of 100ppm. As increasing immersion time, the Ra is increasing. In addition, the line-formed roughness to <110> direction and the local bumps are appeared on the Si(110) surface. However, the Ra of immersion for 1 hour is not almost change from the initial Ra. Moreover, Si atoms eluted in UPW for 24 hours calculated from the decrease of SOI thickness was less than 4.0×1014/cm2 per 1hour. This means that the amount of elution of Si atoms in UPW within 1 hour is less than 1 atomic layer because the areal density of Si(110) orientation substrate is 9.6×1014/cm2 [5]. In the actual wafer cleaning process, the time of UPW attaching to wafer surface is far shorter than 1 hour. Therefore, when the O2 concentration is controlled less than 100ppm in the wafer cleaning process, it can be expected that Si(110) surface of sidewall of 3D transistor is not roughened and the shape of Si fin structure is kept. Furthermore, we evaluate the O2 concentration by using the prototype 200mm single wafer cleaning chamber. We demonstrated that the O2 concentration in this chamber can be decreased less than 100ppm within 1 minute by N2 purge of 200 L/min.AcknowledgementsThis work is based on results obtained from a project commissioned by the New Energy and Industrial Technology Development Organization (NEDO) and was carried out at the Fluctuation Free Facility (FFF) of New Industry Creation Hatchery Center, Tohoku University.Reference[1] D. James, 27th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), pp. 324-329, May 2016.[2] A. Teramoto et al., IEEE Trans. Electron Devices, vol 54, No 6, pp. 1438-1443, 2007.[3] H. Morinaga, et al., Solid State Phenomena, Vol.134, pp.45-48, 2007.[4] K. Nii, et al., 206th Meeting of The Electrochemical Society, 2004.[5] M. Higuchi, et al., Appl. Phys. Lett. 90 Number 12, pp. 123114-1-123114-3, 2007. Figure 1

Guest Editorial Special Section on the 2018 SEMI Advanced Semiconductor Manufacturing Conference

The 2018 SEMI Advanced Semiconductor Manufacturing Conference, the 29th since its conception, was held once again in Saratoga Springs, NY, USA, May 1 through May 3, 2018. Saratoga Springs provided a beautiful backdrop for discussion of the many topics central to the continued success of the semiconductor manufacturing industry in areas including Advanced Metrology, Advanced Processes and Materials, Advanced Process Control, Contamination-Free Manufacturing, Cost Reduction, Equipment Reliability and Productivity, Defect Inspection, Environmental, Health and Safety, Factory Automation and Dynamics, Human Resources Management and Development, Lithography Advances and Challenges, Yield Enhancement, and Yield Modeling. Semiconductor device manufacturers, equipment and materials suppliers, academia, and others all came together these three days, as presenters and attendees, to exchange ideas and insights. Throughout the conference, two parallel session tracks provided options to match the interests of each attendee, without being overwhelming.

Guest Editorial Special Section on the 2016 SEMI Advanced Semiconductor Manufacturing Conference

The past year has brought many reminders that we live in an increasingly digital world. Technology shapes and enhances our lives each day on several fronts. • Shopping from the comfort of our homes. • Ready access to a multitude of information using our smartphones or other kinds of wireless devices, often accessed with the help of voice technology and digital assistants. • Smart control of our homes and offices, saving power, improving comfort, and enhancing our security. • Active driver assistance and accident avoidance features now commonplace in today’s cars. • Development of new, useful, technologies and services such as cyber currency, easy point-of-sale transactions, and the self-service kiosks we use at the supermarket and airport. And there are trends that many of us consider troubling. • Worrisome levels of telephone attachment in today’s teens. • Election hacking and manipulative social media engineering. • Cyber crime such as the WannaCry virus. • Stolen identities.

Poly-Si Planarization by ICP Plasma Etch at FinFET Technology

: The fin field effect transistors (FinFET) have been extensively explored for many years and recently mass production have been realized for its superior properties in solving short channel effects and size-down requirements. [1]In FinFET technology node, the topography started to turn worse due to the introduction of the three-dimensional (3D) fin structures. The control became one of the most important issues in FEoL. In poly-gate loop, the lithography window and poly silicon etch profile will be limited by the surface topography and thus affect the device performance as well as the yield improvement. To improve the poly-silicon topography after the CMP process becomes very important.In this paper, we report the poly-silicon planarization with the introduction of the matrix-temperature controller, named as Hydra, which is equipped in one commercial inductive coupled plasma (ICP) etch tool. The 3sigma of poly-silicon thickness within improved 80% and the uniformity is very close to current planar technology node, as shown in Figure 1. The temperature dependence is 21.7A/℃. The planarization results show better performance than gas cluster ion beam (GCIB) method as reported. [2] For more common use, an advanced process control is also proposed to overcome the difference of incoming after CMP process. The CMP process always shows a major radical thickness map, which can be compensated by tuning radical etch rate map by changing process parameters. The Hydra based etch planarization technology can also be extend to other process as ILD etch back with suitable etch process. This technology will be very power in the future 3D transistors for planarization.This work was partially sponsored by Program of Shanghai Technology Chief Scientist (B type). The authors would like to thank Mr. Kui Wang, Mr. Jiangang Liu, and Dr. Yushan Chi from Lam research for the support of constructive discussion. Reference: [1] C. Auth et al., “A 22 nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors,” in VLSI Symp. Tech. Dig., pp. 131–132, 2012, [2] T. Kagalwala et al., “Integrated metrology's role in Gas Cluster Ion Beam etch”, 26th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), pp. 72-77, 2015 Figure 1

Guest Editorial Special Section on the 2015 SEMI Advanced Semiconductor Manufacturing Conference

Almost one year ago, we sent selected authors who had presented at the SEMI Advanced Semiconductor Manufacturing Conference 2015 the following letter.

Special Section on the 2014 SEMI Advanced Semiconductor Manufacturing Conference

The big picture for the semiconductor industry shows slowing but still positive sales growth, a push back of the transition to 450 mm wafers to perhaps the next decade, and potential commercial implementation of EUV for some layers of some sub-10 nm nodes by 2019–2020. <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1–3</sup> Per Gartner, current revenue growth is driven by smartphones, solid-state drives, and DRAM. <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup> A new semiconductor sector, wearables (smartwatches, smart glasses, Bluetooth headsets, etc.) is also driving some revenue growth but on a smaller scale. Critical to this revenue growth is the ability to deliver ever more powerful semiconductor technologies at a competitive cost.

SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2015)

SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2015)

Editorial Special Section on the 2013 SEMI Advanced Semiconductor Manufacturing Conference

The papers in this special section were presented at the 2013 Advanced Semiconductor Conference (ASMC).

Guest Editorial Special Section on the 2012 SEMI Advanced Semiconductor Manufacturing Conference

The ten papers in this special section are enhanced versions of some of the best papers from the 2012 SEMI Advanced Semiconductor Manufacturing Conference.