Self-routing Interconnection Networks Research Articles

Nonblocking properties of interconnection switching networks

Self-routing interconnection networks with their low processing-overhead delay and decentralized routing, are an attractive option for switching fabrics in high speed networks. These interconnection networks, however, realize only a subset of all possible input-output permutations in a non-blocking fashion. The non-blocking property of these networks is an extensively studied area in interconnection network theory field and efficient algorithms exist to check if any given permutation is passable by such networks without blocking. One of the most common interconnection network structures is the inverse omega network and is topologically equivalent to the reverse banyan network. The authors show how to check the passability by the inverse omega network of any given connection set and list some of the very general patterns passable by this network. They also show that the concentrate operation passable by the inverse omega network is just a special case of the more general alternate sequence operation that they show as being passable. These non-blocking properties will be useful for cell routing in switches built with blocking networks in parallel or in cascade. >

Using recurrent neural networks to learn the structure of interconnection networks

A modified Recurrent Neural Network (RNN) is used to learn a Self-Routing Interconnection Network (SRIN) from a set of routing examples. The RNN is modified so that it has several distinct initial states. This is equivalent to a single RNN learning multiple different synchronous sequential machines. We define such a sequential machine structure as augmented and show that a SRIN is essentially an Augmented Synchronous Sequential Machine (ASSM). As an example, we learn a small six-switch SRIN. After training we extract the network's internal representation of the ASSM and corresponding SRIN.

Generalized schemes for access and alignment of data in parallel processors with self-routing interconnection networks

In this paper, we give a generalized solution to the problem of conflict-free access of various templates of data of a matrix, when they are stored in memory units in a parallel processor. The important features of our method are: (a) compact representation of a skewing scheme, (b) simple address computation, (c) use of self-routing schemes to set up the interconnection network, and (d) a general framework for the study of skewing schemes. In our method, each template access of interest will be a linear permutation on the processor address. The linear permutation involved determines the types of templates accessible. For parallel access of the most important templates, namely, row, column, main diagonal, and square blocks, the interconnection network needs to realize only the class of linear-complement permutations. It is known that with Beneš or Omega as the interconnection network, one can efficiently self-route these permutations; this compares favorably with the schemes proposed by other researchers who assume that a crossbar is available for processor-memory interconnections. Hence, the approach given in the paper can be used to solve the data alignment problem for the existing parallel machines such as IBM RP3, Cedar multiprocessor, and NYU Ultracomputer. This is a generalized solution to the data skewing problem and encompasses the previous efforts by other researchers as special cases.

Considerations of periodic traffic in packet switching

The basic model of packet switching based on a self-routing interconnection network is described. The theory of periodic contention is reviewed, showing that a broadband switch is nonblocking for the periodic traffic type if it is fast enough to avoid the phenomenon of persistent blocking, where an input buffer consistently transmits fewer packets than it is receiving. The necessary and sufficient switch rate for avoiding persistent blocking is determined. This rate turns out to be a more stringent requirement than if the traffic pattern had been Poisson, a usual assumption. >

Design and Performance of Generalized Interconnection Networks

This paper introduces a general class of self-routing interconnection networks for tightly coupled multiprocessor systems. The proposed network, named a "generalized shuffle network (GSN)," is based on a new interconnection pattern called a generalized shuffle and is capable of connecting any number of processors M to any number of memory modules N. The technique results in a variety of interconnection networks depending on how M nd N are factored. The network covers a broad spectrum of interconnections, starting from shared bus to crossbar switches and also includes various multistage interconnection networks (MIN's).