Self-aligned Via Research Articles

Enhanced and Efficient Guiding Template Design for Lamellar DSA With Graph Monomorphism

Lamellar directed self-assembly (DSA) technology in combination with the self-aligned via (SAV) process has emerged as a novel and promising choice for via/contact layer fabrication, where a via between Metal-x and Metal-(x+1) is generated at the intersection of a wire segment on Metal-(x+1) and a rectangular and perpendicular guiding template. Compared to the highly investigated cylindrical DSA, lamellar DSA does not suffer from the overlay error of generated holes and thus can have better yield, and it also benefits from the better flexibility of various via pitches a single template can produce. A state-of-the-art work has addressed the guiding template design problem for the new process, and an integer linear programming (ILP) formulation that can optimally solve the problem as well as a simple heuristic approach are proposed. However, solving the ILP formulation is time-consuming, and the heuristic method suffers from unignorable degradation in solution quality due to several algorithm deficiencies. In this paper, we propose an enhanced and efficient template design algorithm flow for the lamellar DSA and SAV process by using graph monomorphism for pattern conflict check in multiple patterning lithography. Experimental results show that the proposed flow can greatly reduce the numbers of conflicts and short templates and is almost as efficient as the existing heuristic approach.

Area-Selective Deposition of AlOx and Al-Silicate for Fully Self-Aligned Via Integration

The rush for better-performing electronics, and manufacturing processes that heavily rely on "top-down" patterning techniques, is making the integration of "self-aligned" fabrication methods, such as area-selective deposition (ASD), a critical objective for continued device scaling. The fully self-aligned via (FSAV) scheme is broadly proposed as a "killer application" to determine whether ASD can shift from an R&D process to high-volume manufacturing. Nevertheless, the lack of a suitable low-κ deposition process has prevented the realization of FSAV by dielectric-on-dielectric ASD. This is primarily due to the high temperature and/or strong oxidizers employed during low-κ dielectric deposition and their unsuitability in the presence of organic masks, such as self-assembled monolayers (SAMs), used to prevent material nucleation during ASD. In this work, AlOx and Al-silicate atomic layer deposition (ALD) processes are studied to provide suitable materials for ASD-enabled FSAV. Dimethylaluminum isopropoxide and H2O are utilized to deposit the metal oxide, whereas Al-silicate is grown by adding 2,2-dimethoxy-1,6-diaza-2-silacyclooctane (DMDAcO) pulses to the AlOx ALD cycle. The selectivity of such processes is demonstrated on 50 nm Cu/SiO2 structures, using octadecanethiol-derived SAMs to inhibit material nucleation on the metal lines. Scanning and transmission electron microscopies are employed to assess the quality of the ASD processes and investigate the mechanisms behind defect generation on a nongrowth surface. X-ray photoelectron spectroscopy measurements show the high purity of the AlOx film, whereas DMDAcO-ligand incorporation into the Al-silicate matrix is observed. Planar capacitor structures are used to assess the electrical properties of both ASD films, revealing that the silicate film exhibits a relatively low κ-value (5.3 ± 0.2), with a high acceleration field factor (32.4 ± 1.4) and a dielectric breakdown voltage of 6.0 ± 0.3 V at 100 °C.

ASAP5: A predictive PDK for the 5 nm node

We present a predictive process design kit (PDK) for the 5 nm technology node, the ASAP5 PDK. ASAP5 is not related to a particular foundry and the assumptions are derived from literature. It incorporates several innovations that the semiconductor industry has adopted to address scaling challenges, improve reliability and performance. These include contact over active gate (COG), fully self-aligned vias (FSAVs), single diffusion breaks (SDBs), and cobalt interconnects. We discuss implications of these changes in the context of standard cell and static random access (SRAM) bit cells. Interconnect modelling is improved and incorporates the effects of metal fill and barrier geometry on line resistivity. Different metal fill and barrier configurations are compared to determine the PDK interconnect stack. We discuss design rule assumptions for the key layers. The PDK uses horizontal nanowire field-effect transistors (NWFETs) for better ON and OFF-state performance. The transistor compact models are calibrated to the 3-D technology computer-aided design (TCAD) simulation results.

(Invited) Area-Selective Atomic Layer Deposition for Interconnect Applications

As the semiconductor industry is approaching the 5nm node technology, conventional patterning schemes cannot meet the ever-increasing requirements for alignment imposed by device miniaturization. Area-Selective Deposition (ASD) can potentially alleviate such manufacturing challenges by enabling bottom-up material deposition. The most used and successful approach to achieve ASD envisage a combination of Atomic Layer Deposition (ALD) and surface passivation, such as, self-assembled monolayer (SAM).Among the potential applications, dielectric on dielectric (DoD) ASD emerged as one of the most important for multilayer nano interconnects (e.g.: enabling fully self-aligned vias). In this context, along with the difficulties encountered in preserving a confined material growth, the challenges extend to the fact that the deposited dielectric must exhibit well-defined properties, such as low-dielectric constant. Indeed, the integration an interconnect dielectric deposition process in an ASD scheme is arduous. Vapor-phase deposition of SiO2-like materials typically requires high process temperature as well as strong oxidants or O2-plasma. These are not compatible with the organic passivation films exploited to create well-distinguished local surface chemistries, which is essential to enable selective-material deposition.In this talk, 1-octadecanethiol (ODT) well-known selective chemisorption on Cu over SiO2 is exploited to achieve AS-DoD deposition and understand the surface-driven mechanism that enables a selective material growth. In addition, the proposed ASD scheme in combination with nanoscale adhesion force characterization is used to tackle a critical lack in ASD metrology: monitoring the passivation film directly on patterned substrate. Finally, the challenges and results obtained as an ODT-compatible dielectric deposition process for interconnect applications are discussed in this talk.ASD enabled by metal passivation for Hf3N4, Hf-Silicate, Al2O3, and Al-silicate ALD are explored and presented on Cu/SiO2 patterned substrates, with critical dimension as low as 10nm.

Area-Selective Molecular Layer Deposition of a Silicon Oxycarbide Low-k Dielectric

Area-selective deposition (ASD) of low-k materials is desired in back-end-of-line processes for fabricating nanopatterns such as fully self-aligned vias. However, the high temperature and/or aggres...

Area-Selective Deposition by a Combination of Organic Film Passivation and Atomic Layer Deposition

To enable the downscaling of Integrated Circuit (IC) components accordingly to Moore’s law, novel nano-patterning techniques and materials are essential. Self-Aligned patterning schemes, such as Area Selective Deposition (ASD), are receiving increasing attention due to challenges created by the continuous shrinking of critical dimensions (e.g. self-aligned vias to lines in multi-level interconnect architectures). In ASD, a given film is deposited exclusively on the desired growth area with respect to the non-growth area. Typically, this can be achieved by exploiting material properties, such as surface chemical composition variations, in combination with surface-sensitive deposition techniques, such as Atomic Layer Deposition (ALD). In addition, the ALD self-limiting half-cycle surface reactions provide a layer-by-layer growth mechanism, which is strongly dependent upon the chemical reactivity to the underlying layer. Intrinsic growth nucleation variations on different surfaces can be exploited in an ASD scheme, but this effect is typically limited to very few ALD cycles. In this talk, Self-Assembled Monolayers (SAMs) are evaluated as a passivation coating to extend the ASD process window. Potential applications that will be discussed are Copper passivation in a self-aligned via patterning process flow and area-selective bottom-up VIA fill in an interconnect metallization scheme.

Extending the compositional diversity of films in area selective atomic layer deposition through chemical functionalities

As the semiconductor community continues scaling, area selective atomic layer deposition (ASD) offers the potential to relax down stream processing steps by enabling self-aligned processes (e.g., self-aligned vias). Otherwise, conventional means of lithography face increasingly difficult challenges such as patterning and overlay errors as resolution improves. ASD can be achieved under a variety of conditions, and with the use of organic inhibiting materials, it can exhibit some of the highest levels of selectivity. However, the structure property relationship of these inhibiting materials is not completely understood, and therefore the relationship between a materials chemical functionality and its inhibiting properties remains largely unexplored. This was explored with polymeric materials that served as a versatile materials platform allowing a broad variation of chemical functional groups and physical properties that may then enable the ASD community to extend the number and types of films that can be selectively deposited. Initially, hydrophobic polymers including polystyrene (PS) and polyvinyl chloride (PVC), as well as an oleophobic polymer, poly[difluoro-bis(trifluoromethyo)-dioxole-co-tetrafluoroethylene] (PTFE-AF), were surveyed for their inhibitory properties toward the atomic layer deposition of industry relevant metal oxides such as Al2O3 and TiO2, which heavily feature as etch masks and other functional nanostructures. Despite blanket deposition of Al2O3 being observed, even when using an oleophobic polymer such as PTFE-AF, TiO2 deposition was notably inhibited by blanket films of PVC, PS, and PTFE-AF. In light of these results, the functionalization of PVC and PS with selective area substrate anchoring groups such as phosphonic acids (targeting copper oxide surfaces) was conducted to investigate whether grafting selectivity of these polymer films to their intended surface could be inhibited, thereby achieving film growth in the proximal uninhibited area. Two methods of polymer functionalization were evaluated: phosphonic acid groups distributed randomly throughout the polymer backbone of PVC and a single phosphonic acid group localized at the chain end of PS. Notably, the PVC multidentate derivatives and the PS monodentate type polymers exhibited effective inhibition of TiO2.

Via Bottom Profile Optimization in All-in-One Etch with Double Patterning Scheme

—In advanced CMOS technology node with Cu/low-K interconnection, double patterning scheme with Metal Hard-Mask (MHM) All-In-One (AIO) etch is used to define smaller via and trench. The bottom profile of via is critical for via connectivity and RC delay. Tapered via bottom profile means smaller contact area with lower metal which means larger via contact resistance and degradation of chip interconnect performance. The bottom profile of via may probably become tapered when it enters Etch Stop Layer (ESL) or when the plasma touches lower Cu layer. In this paper, we will explain the reason of tapered via bottom profile and several ways to solve this problem. Keywords—AIO etch; Via bottom taper profile; ESL; Cu exposure; Metal capping layer; Introduction—In current LELE double patterning scheme, the partial via (PV) is firstly formed in 1st mask. Then the second PV is formed in 2nd mask, following by one in-situ ash which will remove PR tri-layer film. Then AIO etch will form via bottom and hard mask defined trench pattern at one etch process synchronously. MHM pattern is also defined by LELE double patterning before PV etch. The process sequence is briefly depicted in Fig.1. In our process, via is self-aligned by MHM for photo lithography reaches its limit on via. After photography critical dimension (CD) is quite large, via CD is shrunk during tri-layer etch process. After shrinking, Via CD is still larger than line CD. Therefore, we use self-aligned via (SAV) to confine via in MHM open area to ensure final VBD and TDDB performance acceptable. In this scheme, we should ensure MHM selectivity during whole etch process to let it not be etched through. Porous ultra-low-k (ULK) is introduced to reduce interconnect RC delay [1]. The etch stop layer (ESL) is introduced to balance different patterns’ loading after PV and trench etch. Then we used a LRM step to open ESL and touch lower Cu layer. However, we found the via bottom profile inside ESL is usually tapered. The tapered via profile into ESL could result in decreased contact area to lower metal Cu which is critical to final RC value. The plasma etch rate in ESL is always relatively slow to make sure the former PV and trench etch step can stop on it. For the practical ULK and ESL film thickness in advanced technology node, the selectivity ULK to ESL should be at least 5 to ensure 80-90% percentage of trench depth is etched by trench etch step, and the following ESL opening step just remove the little trench depth remaining [2]. In final Liner Remove (LRM) step, the etch rate cannot be so fast, meanwhile the etch rate (ER) will be slower after Cu exposure. In fluorocarbon plasma with oxygen, oxygen captures carbon to form C-O bond and control the polymer generation. Such ER change is induced by the reduction of oxygen ion after Cu exposure which will affect the total etch performance to form tapered via bottom profile. In this paper, tradition way to change plasma condition, the change of ESL and the introduction of lower metal capping layer will be used to solve via bottom tapered issue.

Modeling of Via Resistance for Advanced Technology Nodes

We investigate the dependence of Cu via resistance on via dimensions, shape, misalignment, and Co via prefill level by means of a novel resistivity model, calibrated to actual wires on silicon and integrated into the Synopsys Raphael tool. For this paper, we consider the case of 16 and 12nm self-aligned vias, which are representative for the 7 and 5nm logic technology nodes, respectively. Process emulations are performed by using the Synopsys Sentaurus Process Explorer tool in order to generate 3-D models of the investigated via structures. Finally, via resistance is extracted through current simulations in Raphael, that is, by taking into account the actual conductive path from the wires into the via. We predict that via resistance could increase by more than a factor of 2 from node to node. We show that chamfered vias can exhibit up to 56% less resistance than standard (87° tapered) vias because of the larger cross section at the via top. For the same reason, via resistance sensitivity to via width variations along the direction of the connecting (i.e. upper) wire is smaller for chamfered vias. As far as via misalignment to the connected (i.e. lower) wire is concerned, we demonstrate that in the range of interest, the induced resistance increase is not severe (e.g. 20% or lower), and in particular, via resistance is not inversely proportional to the contact area between the via and the connected wire. If side contact to the connected wire is enabled upon misalignment, the via resistance increase is further reduced. If vias are fully self-aligned, that is, self-aligned to both connecting and connected wires, the impact of misalignment can be neutralized in a certain range by properly oversizing the via mask in the direction along the connecting wire. Finally, we show that Co via prefill can enable a substantial reduction (up to 45%) of via resistance for chamfered vias, where the bottom barrier surface can be significantly increased when raised to the via top by means of the prefill step.

Potential CCP Pulsed Plasma Application at Beol AIO Etch Process

Plasma etching has been extensively used for more than 30 years in semiconductor manufacturing industry [1]. Typically, plasma reactor RF power sources have constant average power to excite the plasma in a vacuum chamber. Such mode of operation is termed as continuous-wave (CW) RF mode [2]. As COMS is being scaled down to 28nm node and beyond, CW plasmas etching processes are reaching their limits to satisfy the multiply stringent requirements, such as better uniformity, higher selectivity, less plasma induced damage, tighter critical dimension and profile control. The RF pulsed plasma is one of promising knobs to increase the flexibility of plasma processing by enlarging the range of operating conditions [3-5]. There are two main parameters characterizing the RF pulse: one is the pulsed frequency at which the RF power is turned on and off per second; the other is the pulse duty cycle, which is defined as the ratio between the pulse on time and the total pulse duration. As the multiple-frequency RF powers have been introduced for the better control plasma flux and energy in CCP system, the effect of different RF power pulsing varies, bias only, source only and synchronized pulsed plasmas also shows quite different performances. In this work, self-aligned via (SAV) based all-in-one (AIO) etch processes were performed in one commercial etcher, and the effects of pulsed plasmas on the etch process were analyzed. The different pulsed mode, pulsed duty cycle, pulsed frequency on CCP chamber were tested on the SAV based AIO etching process in BEOL copper interconnect system. We compared the bias only, source only and synchronized pulsed plasma performances, checked the duty cycle effects, which varies from 10% to 90%. The Physical performances were analyzed by CDSEM, SEM, TEM, and TK. Compared with conventional CW plasmas, the performances of AIO etching process could be significantly improved via pulsed plasma, such as more rounding chamfer profile, via bottom CD control, and better SAC process with higher selectivity to metal hard mask. Acknowledgement This work is sponsored by Shanghai Rising-Star Program (B type). REFERENCES [1] S. Banna, A. Agarwal, G. Cunge, M. Darnon, E. Pargon, and O. Joubert. J. Vac. Sci. Technol. A, vol. 30, 2012, pp. 040801. [2] S. Banna, A. Agarwal, K. Tokashiki, H. Cho, S. Rauf, V. Todorow, K. Ramaswamy, K. Collins, P. Stout, J. Y. Lee, J. Yoon, K. Shin, S. J. Choi, H. S. Cho, H. J. Kim, C. H. Lee, and D. Lymberopoulos. IEEE Trans. Plasma Sci., vol. 37, 2009, pp. 1730-1746. [3] R. W. Boswell and D. Henry. Appl. Phys. Lett., vol. 47, 1985, pp. 1095-1097. [4] P. Subramonium and M. J. Kushner. Appl. Phys. Lett., vol. 79, 2001, pp. 2145-2147. [5] A. Rousseau, E. Teboul, N. Lang, M. Hannemann, and J. Ropcke. J. Appl. Phys., vol. 92, 2002, pp. 3463-3471.

TiN Hard Mask Cleans with SC1 Solutions, for 64nm Pitch BEOL Patterning

Titanium Nitride metal hard mask was first introduced for BEOL patterning at 65 nm [1] and 45 nm nodes [2]. Indeed, in this “Trench First Hard Mask” (TFHM) backend architecture, the dual hard mask stack (SiO2 & TiN) allows a minimized exposure of ULK materials to damaging plasma chemistries, both for line/via etch sequence, and lithography reworks operations. This integration scheme was successfully used for a BEOL pitch down to 90 nm for the 28 nm node, however, for the 14 nm technology node, 64 nm BEOL minimum pitch is required for the first metal levels. Because it is unable to resolve features below 80 nm pitch in a single exposure, conventional 193 nm immersion lithography must be associated with dual patterning schemes, so called Lithography-Etch-Lithography-Etch (LELE) patterning [3] for line levels and self-aligned via (SAV) process [4] for via patterning. In both cases, 2 lithography/etch/clean sequences are necessary to obtain one desired pattern, and associated reworks also become more challenging since first pattern is exposed to resist removal processes (plasma + wet clean). The reference wet cleans that were developed for 65 to 28 nm TiN hardmask patterning, utilizes commonly used chemistry for BEOL post-etch cleans, i.e. diluted hydrofluoric acid (dHF) followed by deionized water Nanospray (DIWNS) on 300 mm single wafer tool.

Industrial Challenges of TiN Hard Mask Wet Removal Process for 14nm Technology Node

TiN Hard Mask (TiN-HM) integration scheme has been widely used for BEOL patterning in order to avoid ultra low-k (ULK) damage during plasma-ash process [1]. As the technology node advances, new integration schemes have to be used for the patterning of features below 80 nm pitch with 193 nm immersion lithography. In particular, thicker TiN-HM is necessary in order to ensure Self-Aligned-Via (SAV) integration which resolves via-metal short yield and TDDB issues caused by Litho-Etch-Litho-Etch (LELE) misalignment [2, 3]. The Cu filling process is significantly more difficult if the thick TiN is not removed because of the high aspect ratio of the structures. Moreover, with the use of TiN hard mask, a time-dependent crystal growth (TiCOF) residue may forms between line etch and metal deposition [4, 5], also hindering copper filling. Post-Etch-Treatment after line etching is one solution to the problem but N2plasma is not efficient enough to suppress the residue completely [6], and the CH4treatment proposed in [5] may be difficult to implement for 14 nm node, thus an efficient wet strip and clean provides a better solution.

A Study of Self-Aligned-Via Based All-in-One Etch

Trench-first-metal-hard-mask (TFMHM) approach has been widely utilized together with punch-through-via (PTV) scheme for copper interconnect formation since sub-65nm CMOS technology node. In this work, compared to the traditional PTV scheme on sub-45nm test vehicle, we successfully demonstrate that the self-aligned-via (SAV) based all-in-one (AIO) etch process could be fulfilled on thin metal hard-mask and is capable of delivering much better via related TDDB performance without the performance degradation of electromigration (EM), while the contact resistance (Rc) exists different trend with PTV scheme. The high etch selectivity is imperative in both partial via etch, trench etch and liner removal step to reduce the via encroachment on metal hard-mask, the via CD along the unconfined (metal hard-mask) direction should be also optimized to achieve the above desired performance without tiger teeth beneath via bottom. Both via and trench etch recipe need be well optimized to deal with etch stop, via bottom grass and polymer residue issues. Besides, SAV delivers much good yield performance even at misalignment via chain test key, which indicates its very robust overlay margin. But it suffers yield loss at some sub-rule test structure in which trench line end CD is strictly confined by nearby pattern.

The Optimization of Metal Hard-Mask Based All-in-One Etch

Metal hard-mask based all-in-one etch scheme has been extensively integrated with Cu interconnects for its significant improvement in terms of the line sidewall roughness, the reduction of ultra low-k material damage and the enhancement of lithography process window. In this paper, we investigated the trade-off relationship between electromigration (EM) and time-dependence break-down (TDDB) on one AMEC (Advanced Micro-fabrication Equipment Company) test vehicle. This etcher features the special switchable rf-power at bottom electrode. Results indicate the dynamic ESC (electrostatic chuck) is imperative to meet the quite different temperature demands between via etch and trench etch step, thus reducing the via encroachment on metal hard-mask while no metallic residue is detected at trench bottom. Meanwhile, the tunable edge ring coupled with the optimization of trench etch gases are also critical to deliver the on-target Rc and reliability performance. In brief, we successfully demonstrated the partial SAV (self-aligned via) could deliver the on-target WAT and reliability performance on AD-RIE.

56 nm pitch Cu dual-damascene interconnects with self-aligned via using negative-tone development Lithography-Etch-Lithography-Etch patterning scheme

In the attempts to push the resolution limits of 193nm immersion lithography, this work demonstrates the building of 3 metal level 56nm pitch copper dual-damascene interconnects, using Negative-Tone Development Lithography-Etch-Lithography-Etch (LELE) Patterning at line level. Line Resistance and intra-level capacitance can be affected by the double patterning integration, but a good process window has been demonstrated, showing no impact on RC performance. The introduction of a self-aligned via (SAV) process with a TiN hard-mask is able to provide a robust process window in terms of via-metal short yield at line and via level. SAV implementation at these dimensions also affects the aspect-ratio of the structures and leads to new challenges in metallization: optimized profile, without bowing or undercut, is mandatory to enable the filling of 28nm lines. The metal hard-mask has to be removed or at least faceted by erosion. This can be achieved by conventional RIE process optimization, but pushes the RIE selectivity to challenging limits. Physical dimensions on target and via chain yield have been demonstrated by fine tuning RIE process. Profile improvement can also be achieved by the introduction of new WET process, helping the removal of the metal hard-mask while being neutral to the ULK. We have demonstrated good yield and reliability with an integration using hard-mask wet removal.

The Effect of Via Patterning Scheme and Metal Hard-Mask Based All-In-One Etch on Contact Resistance of Cu/low-k Interconnects

The impact of via patterning scheme and all-in-one (AIO) etch on contact resistance (Rc) is extensively investigated in this contribution. The addressed tri-layer via patterning schemes consist of CVD-based approach I and spin-on-based approach II. The self-aligned via (SAV) etch method is considered and compared with punch-through (PT) method for the sake of via encroachment concern. Results show both etch methods could deliver the on-target Rc performance with approach I if the overlay shift is strictly controlled and SAV is quite sensitive to overlay shift and could degrade the overall Rc performance if coupled with approach II. The importance of via circularity, trench-etch and post etch treatment (PET) also needs special attention. Besides, wet etch still plays a critical role in achieving the desired Rc. It's imperative to use the alternative wet method other than traditional dilute HF.