Self-aligned Triple Patterning Research Articles

A Gridless Approach to the Satisfiability of Self-Aligned Triple Patterning

Self-aligned triple patterning (SATP) lithography is one of the most promising technologies for next-generation semiconductor manufacturing process. Self-aligned patterning attracts much interest because of its significant advantage over the litho-etch-litho-etch patterning in reducing the overlay problem in lithography. However, pattern decomposition in SATP is challenging due to its counterintuitive mask synthesis. It remains relatively unstudied and its practical solutions remain to be proposed. This paper proposes an effective algorithm for SATP layout decomposition without grid-based quantization and thus substantially reduces the number of variables and constraints in solution search. Boolean satisfiability (SAT) and integer linear programming (ILP) are exploited for efficient computation. In addition to deriving high-quality layout decomposition solutions with overlay minimization, our method also allows nondecomposable spot identification to facilitate layout rectification. Experimental results demonstrate the superiority of our method compared to prior work and show the relative advantages of SAT and ILP formulations.

Litho-Friendly Decomposition Method for Self-Aligned Triple Patterning

Multiple patterning lithography is the most likely manufacturing process for sub-32 nm technology nodes. Among different multiple patterning methods, self-aligned patterning has attracted much interest due to its robustness against overlay errors. However, self-aligned patterning compliance is subject to the litho-friendliness of the applied decomposition method. This brief establishes self-aligned triple patterning (SATP) decomposition requirements and proposes a litho-friendly layout decomposition method. First, the major SATP litho-friendliness requirements are explained. In-silico experiments on SATP process indicate that layout features printed by the structural spacers are the most accurate ones. Therefore, we propose an ILP-based decomposition which avoids decomposition conflicts and maximizes the use of structural spacers simultaneously. Experiments reveal that the proposed method improves overlay robustness and line-edge roughness of the attempted test cases.

(Invited) Optical Lithography Extension Technique with Multiple-Patterning Process

The double patterning process has become a technology for extending the life of 193-nm immersion lithography. It is the most useful techniques of advancing downscaling in semiconductors and can theoretically be used scale infinitely down. For the self-aligned type of double patterning, such as self-aligned double patterning (SADP), self-aligned triple patterning (SATP), and self-aligned quadruple patterning (SAQP)[1], we have reported that spacer-pattern processing is more difficult than line-pattern processing since the former includes more fluctuating factors, and that improving the performance of the core pattern is essential to solving this problem. Similarly, as calls for even more improvement in line edge roughness (LER) have come to be made, we have investigated the relationship between the core pattern and LER. Thus, given the importance of finding a means of securing pattern fidelity in the core pattern to improve critical dimension uniformity (CDU) and LER,we improved resist contrast resulting in dramatically reduced LER and improved spacer CD uniformity over the wafer surface. This paper presents the results of observing pattern fidelity in the double patterning process from many aspects and the results of testing a technique for high-accuracy management of pattern fidelity.

Process optimization and simplification of self-aligned triple patterning

Graphical abstractDisplay Omitted Highlights? A wet trimming process was developed to shrink mandrel line CD in SATP technique. ? The wet process smoothes out high-frequency components of LER. ? A selective dry etch is used to release the sacrificial spacers. ? CDU and LWR performance have been significantly improved. ? The first full-wafer 18nm L/S CDU and LWR data were reported. Self-aligned triple patterning (SATP) technology offers both improved resolution and design flexibility for scaling integrated circuits down to sub-15nm half pitch. By keeping and designing mandrel patterns which further define the route of the following spacers, SATP process represents a prospective trend that not only drives up the feature density, but also relaxes the overlay requirement with fewer masks and allows quasi-2D design flexibility. In this paper, we shall present the latest research progress made in optimization of existing SATP process to improve its lithographic performance such as CDU and line width roughness. In addition to solving the previously reported problems of etching small mandrels and sacrificial spacers, we also address the issue of reducing SATP process complexity/cost.