Second-order All-pass Sections Research Articles

High-order allpass cascade-connected phase-system design utilizing fractional polynomial errors

ABSTRACT This paper proposes a nonlinear optimization method for designing a high-order recursive allpass digital phase system that comprises several cascade-connected second-order (SO) allpass sections. This method first splits a given phase design specification (approximation target) into a set of equal sub-specifications, and then the equal sub-specification acts as the ideal phase for each of the SO sections. Since an SO section can be designed via employing a linear programming to minimize a linear fractional error function, this splitting process generates an excellent starting point (good initial values for the coefficients of the cascaded SO sections) for further minimizing the overall approximation error. This paper first derives a wide variety of fractional polynomial error functions for designing cascade-connected allpass phase systems of different high orders, and then shows that a high-order cascade-connected allpass phase system can be designed by utilizing a nonlinear solver to minimize the peak deviation of such a fractional polynomial error. Using the derived fractional polynomial error functions in the system design enables the system designer to find an excellent starting point for further minimizing the approximation error and thus reach a convergent design solution. This paper first derives a set of fractional polynomial errors, and then adopts the eighth-order cascade-connected phase system design to exemplify the effectiveness of the fractional-polynomial-error-based design tactic. Furthermore, the stability of the cascade-connected high-order allpass system can be readily checked via confirming that all of the cascaded SO sections have their poles inside the unit circle in the complex plane.

Dispersive Delay and Comb Filters Using a Modal Structure

High-order dispersive delays are typically implemented as a cascade of second-order allpass sections, making them difficult to modify in real time and prone to numerical issues. Here, such filters are implemented using a modal architecture—a parallel combination of resonant filters tuned to a set of mode frequencies determined by the desired dispersion characteristic. Two configurations are presented, a “dispersive delay filter” in which a single dispersive arrival is produced, and a “dispersive comb filter” in which a series of increasingly dispersive echoes of the input signal are generated. The parallel structure has computational and numerical advantages. Simple, closed-form techniques for designing the needed mode filter frequencies and amplitudes according to the desired dispersion and equalization are presented, and applied to spring reverberator emulation and decorrelation filter design.

VLSI Implementation of Lattice Wave Digital Filters Using Fixed Point Arithmetic for Increased Maximum Sampling Frequency

VLSI Implementation of Lattice Wave Digital Filters Using Fixed Point Arithmetic for Increased Maximum Sampling Frequency Low complexity and high speed are the key requirements of the digital filters. These filters can be realized using all-pass sections. In this paper, design and minimum hardware implementation of a fixed point lattice wave digital filter based on three port series adaptor is proposed. Here, the second-order all-pass sections are replaced with three port series adaptors. A design-level area optimization is done by converting constant multipliers into shifts and adds using canonical signed digit (CSD) techniques. The proposed implementation reduces the latency of the critical loop by reducing the number of components (adders and multipliers).

Accuracy improvement of real-poles allpass-based digital Hilbert transformers

In this work a very efficient approach to extend the frequency range over which the real-poles allpass-based digital Hilbert transformers (HT) phase difference is kept near constant and to reduce the deviation of the phase from 90º in a limited word-length environment is proposed. This approach is based on minimisation of the phase sensitivity of each individual first- and second-order allpass section in the cascade realisation of the two branches of the structure used, depending on their transfer function pole positions, including replacements of second-order-sections by two first-order low-sensitivity allpass sections. The effectiveness of the proposed design is experimentally verified and the HTs so obtained are very suitable for different telecommunication applications.

Efficient parametric fault detection in switched-capacitor filters

Advances in technology and IC design techniques have allowed for sophisticated analog and digital functions in a single chip, in which switched-capacitor (SC) networks perform fundamental operations such as filtering and A/D and D/A conversion. As a result, considerable effort has gone into improving test coverage and testable circuit design in general and SC networks in particular. This article presents an alternative SC-filter-testing methodology, which not only accurately detects but also locates parametric faults, using little additional circuitry. Based on structurally all-pass building blocks, the proposed technique fits into the DFT category. It uses considerably less additional circuitry for testing than other approaches because the testing procedure consists of forming notch filters out of existing second-order all-pass sections. Moreover, it does not require reconfiguration of the circuit under test, making it suitable for online testing. The testing scheme also belongs to the multifrequency analysis class, but it requires neither optimization nor sensitivity computations because the filter transfer function's synthesis procedure naturally reveals the optimum test frequencies and nodes. The scheme is readily extendable to other discrete- or continuous-time structures based on all-pass filters.

Efficient Algorithm for the Design of High-Speed Elliptic IIR Filters

Abstract The total latency of the arithmetic operations in the critical direct loop of the second-order all-pass IIR section is reduced using a special class of the elliptic transfer function and thus the maximum sample frequency is increased. This is achieved by implementing one of two multipliers per section as a binary shifter, that is, without any hardware in FPGA or VLSI implementations. The second multiplier is implemented with a small number of shifters and adders using the quantization of the coefficients and optimization. We derive new exact formulae for those coefficients and we avoid all unnecessary computations in the optimization. New exact formulae provide efficient, very fast, simple and highly accurate algorithm suitable for standard software packages such as MATLAB. An example of high-speed two-channel filter bank illustrates the application.

Design of IIR multiple notch filters based on all-pass filters

A new method for the design of multiple notch fitters is presented using an all-pass filter of order 2N, N being the number of notch frequencies. The all-pass filter is realized as a cascade of N second-order all-pass sections. Besides meeting the notch frequency specifications exactly, the method ensures that the realized 3-dB bandwidths are lower than those specified. Illustrative examples are given.

Design of multiplierless elliptic IIR filters with a small quantization error

We present a new technique for the design of multiplierless IIR elliptic filters. The multiplierless filter has all multiplication constants implemented with a small number of shifters and adders. The proposed technique is based on sensitivity analysis. An analytical expression for amplitude response sensitivity is derived for the filter structures consisting of two allpass subfilters in parallel. It is shown that the amplitude response sensitivity to some constant x can be expressed as a product of the filter reflectance function and the phase sensitivity of the allpass section that implements the constant. The closed-form expressions for the phase sensitivities of the first- and second-order allpass sections are also developed. It is shown in the paper that the (n+1)/2 most sensitive constants can be directly controlled by the transfer function parameters if the transfer function is derived by the bilinear transformation from an elliptic minimal Q-factors (EMQF) analog prototype. This way, (n+1)/2 multiplication constants can be implemented without quantization, leaving the filter characteristic strictly elliptic. This is achieved for a class of low-noise allpass sections and for the wave lattice digital filter as well. The quantization of the remaining (n-1)/2 less-sensitive constants is performed using the phase-tolerance scheme and phase-sensitivity functions. The proposed design technique is straight-forward and, consequently, very fast. The application is demonstrated on the examples of narrowband, wideband, and halfband filters.

Design of computationally efficient elliptic IIR filters with a reduced number of shift-and-add operations in multipliers

In this paper, a new design method for elliptic IIR filters that provides the implementation of half of the multiplication constants with few shifters and adders is proposed. An IIR filter, when derived by the bilinear transformation from an elliptic minimal Q-factor analog prototype, has its z-plane poles on the circle that is orthogonal to the unit circle and has the center on the real axis of the plane. Due to this property, the center of the circle can be used as a parameter for the representation of a pole, whereas the second parameter is the radius of the pole. It is shown in this paper that the center of the circle is uniquely determined by the frequency for which the filter attenuation is 3 dB. This result is used for the realization based on the parallel connection of two all-pass networks. It is shown that all second-order all-pass sections can be implemented with one common multiplication constant determined by the center of the circle. The design method is presented that, by an appropriate distribution of a margin in the filter performance, predetermines the value of the common constant according to the desired number of shift-and-add operations. This way, half of the multipliers are replaced with a limited number of shifters and adders. Conventional computer programs for IIR elliptic digital filters can be used. The direct approach for the distribution of the z-plane poles among two all-pass functions is developed. The application and efficiency of the proposed design method are demonstrated by examples.

Realisation of lattice wave digital filters using three-port adaptors

The second-order allpass section is the main building block of the lattice wave digital filter (LTWDF). This is conventionally realised using two-port adaptors. The authors present a comparison between the two-port realisation of the second-order allpass section and another based on the three-port series adaptor. It is shown that the sample rate of LTWDFs can be increased by up to 90% with the three-port realisation.

Signal processor implementation of digital all-pass filters

The implementation of digital filter structures of all-pass subfilters using modern high-speed signal processors is investigated. The focus is on digital all-pass filters realized as a cascade of first- and second-order all-pass sections. Wave digital all-pass sections are considered, with special emphasis on developing two-port adaptor structures that are suitable for signal processor implementation. Explicit formulas are developed for scaling and round-off noise analysis of these all-pass sections. Other well-known first- and second-order all-pass filter sections are considered. The performance of the various all-pass filter structures are compared with respect to roundoff noise, parasitic oscillations, and speed of signal processor implementation. >

Simplified design of high-order recursive group-delay filters

A new, simplified method is presented for the design of group-delay filters. The method is derived assuming that the filter order is large and that the filter group-delay function is smooth. Satisfactory results, however, are achieved even if both of these assumptions do not apply. The method permits the realization of filters that are equal ripple approximations to the smooth portions of given group-delay characteristics. The filters are constructed from second-order all-pass sections in cascade. Examples of linear group-delay, quadratic group-delay, and stair step group-delay filters are presented. The design method is simple enough to be implemented with dedicated hardware.

Digital all-pass networks

A systematic method is outlined to realize an m th-order all-pass digital transfer function using only m multipliers as a cascade of first-order and/or second-order all-pass sections. The realization is based on the multiplier extraction approach in which the n th-order filter section is considered as a digital (n + 1) -pair of which n pairs of input and output terminal variables are constrained by n multipliers. The transfer matrix parameters of the digital (n + 1) -pair, containing only delays and adders, are first identified from which the realization is obtained by inspection. Both canonic and noncanonic realizations are derived. All realizations are then compared with regard to the effect of multiplication roundoff and hardware requirements.