Second-generation Current Conveyor Research Articles

0.35 V Subthreshold Bulk-Driven CMOS Second-Generation Current Conveyor

This study describes a high-performance second-generation Current Conveyor (CCII) operating at 0.35 V and achieving rail-to-rail operation at the Y terminal and class AB current drive at the X and Z terminals. The solution utilizes a low-voltage subthreshold bulk-driven CMOS OTA that was experimentally developed earlier, making systematic use of body terminals to improve small-signal and large-signal performance. The circuit has a high open-loop voltage gain and uses cascoded current mirror topologies, resulting in precise voltage and current transfer with bandwidths of 1.33 MHz and 2.13 MHz, respectively. The CCII offers a linear current drive up to 2.5 µA while consuming a total quiescent current of 2.86 µA (758 nA in the output branches), displaying one the highest figures of merit in terms of current utilization for sub 1 V solutions.

0.35 V Subthreshold Bulk-Driven CMOS Second-Generation Current Conveyor

This study describes a high-performance second-generation Current Conveyor (CCII) operating at 0.35 V and achieving rail-to-rail operation at the Y terminal and class AB current drive at the X and Z terminals. The solution utilizes a low-voltage subthreshold bulk-driven CMOS OTA that was experimentally developed earlier, making systematic use of body terminals to improve small-signal and large-signal performance. The circuit has a high open-loop voltage gain and uses cascoded current mirror topologies, resulting in precise voltage and current transfer with bandwidths of 1.33 MHz and 2.13 MHz, respectively. The CCII offers a linear current drive up to 2.5 µA while consuming a total quiescent current of 2.86 µA (758 nA in the output branches), displaying one the highest figures of merit in terms of current utilization for sub 1 V solutions.

A new CMOS-memristor based D-latch with fewer components

In order to study the function of memristor in new devices, a new D-latch is proposed in this paper, which is composed of threshold-type memristor, transistor, resistor and NOT gate. The proposed D-latch uses fewer components than previous. The transistor controls the on-off of the signal, and NOT gate changes the resistance state of memristor. The voltage divider circuit composed of memristor and resistor realizes the latching function. To verify the D-latch, a modified threshold-type memristor emulator circuit (MEC) is proposed. The proposed MEC is composed of operational amplifier, multiplier and second-generation current conveyor. The MEC is a voltage-controlled memristor that can realize floating input. The equivalent resistance of MEC has two kinds of high resistance and low resistance, which change with the polarity of the voltage. The MEC has the characteristic of non-volatility, that is, the resistance state of the circuit remains when the input signal is withdrawn. Through simulation analysis and experimental verification, both circuits have good performance.

1 V Electronically Tunable Differential Difference Current Conveyors Using Multiple-Input Operational Transconductance Amplifiers.

This paper presents electronically tunable current conveyors using low-voltage, low-power, multiple-input operational transconductance amplifiers (MI-OTAs). The MI-OTA is realized using the multiple-input bulk-driven Metal Oxide Semiconductor transistor (MIBD-MOST) technique to achieve minimum power consumption. The MI-OTA also features high linearity, a wide input range, and a simple Complementary Metal Oxide Semiconductor (CMOS). Thus, high-performance electronically tunable current conveyors are obtained. With the MI-OTA-based current conveyor, both an electronically tunable differential difference current conveyor (EDDCC) and a second-generation electronically tunable current conveyor (ECCII) are available. Unlike the conventional differential difference current conveyor (DDCC) and second-generation current conveyor (CCII), the current gains of the EDDCC and ECCII can be controlled by adjusting the transconductance ratio of the current conveyors. The proposed EDDCC has been used to realize a voltage-to-current converter and current-mode universal filter to show the advantages of the current gain of the EDDCC. The proposed current conveyors and their applications are designed and simulated in the Cadence environment using 0.18 μm TSMC (Taiwan Semiconductor Manufacturing Company) CMOS technology. The proposed circuit uses ±0.5 V of power supply and consumes 90 μW of power. The simulation results are presented and confirm the functionality of the proposed circuit and the filter application. Furthermore, the experimental measurement of the EDDCC implemented in the form of a breadboard connection using a commercially available LM13700 device is presented.

Three inputs and one output voltage-mode universal biquadratic filter using one CCII and one CCIII

A voltage-mode universal biquadratic filter using one second-generation current conveyor (CCII), one third-generation current conveyor (CCIII), two capacitors and two resistors is presented. The proposed voltage-mode biquadratic circuit has three input terminals and one output terminal and can realize all the standard filter functions that are highpass, bandpass, lowpass, notch and allpass filters without changing the circuit topology. Both its active and passive sensitivities are small. The proposed circuit does not need one more active component for the unity-gain inverting of the input signal in each filter realization.

Second Generation Current Controlled Current Conveyor Based Low Pass Filter Design For The Processing of EEG Signals

EEG signals are noisy signals that allow brain activity to be analyzed. In recent years, it has been seen that current conveyor-based circuits, which have many advantages such as wide bandwidth, high linearity, low power consumption, have been used instead of operational amplifiers in the analysis of these signals. In this study, a second-generation current controlled current conveyor (CCCII+) low pass filter circuit with a cut-off frequency of 100 Hz has been presented for the analysis of EEG signals. The simulation of the circuit was carried out with the Orcad pspice program. In addition, the application circuit of this low-pass filter circuit has been made and oscilloscope images have been obtained for some frequency values. AD844 IC is used as current conveyor in the application circuit. The data of epilepsy patients and normal people taken from the University of Bonn were applied to the CCCII+ low pass filter circuit and the frequency bands of these signals were examined. It has been predicted that if this CCCII+ low pass filter circuit is used in EEG measurements, it will give good results in the diagnosis of neurological diseases such as epilepsy.

Optimal design of BiCMOS second generation current conveyor using the genetic algorithm

This article presents an innovative implementation of the plus-type second-generation current conveyor (CCII+) using BiCMOS technology, which combines the benefits of bipolar and CMOS technologies. The optimization problem of minimizing the X-port input resistance and maximizing the current cut-off frequency value was solved using genetic algorithm (GA). The proposed approach allows the optimization of the BiCMOS CCII+ to achieve better performance compared to previous designs. As a practical application, a second-order band-pass filter using the optimized BiCMOS CCII+ was successfully realized. The performance of the proposed design was evaluated using SPICE simulations and compared with previously published works. This study shows that the BiCMOS CCII+ can be effectively optimized using GA to improve its performance, which has potential applications in various analog and mixed-signal circuits.

Design and Implementation of Self-Limiting Two-Stage LC Oscillators Using Cascade Structure of Monolithic CCIIs as Active Elements

This paper presents the structure and principle of operation of two circuit configurations of self-limiting LC oscillators using monolithic positive second-generation current conveyors (CCII+s), that are implemented using Current-Feedback Operational Amplifiers (CFOAs) with an available compensation pin (Z). The proposed LC oscillators are synthesized using a systematic approach in the design of analog electronic circuits and can be considered as variants of the basic three-point oscillators, implemented using transistors (BJTs or FETs). Based on the analysis of the structure and electrical parameters of the CFOAs with a compensation pin (Z), electronic circuits of oscillators with two-stage amplifier blocks are synthesized. The characteristic equations and self-oscillation conditions are derived for the obtained analog circuits, and recommendations for designing circuits with arbitrary frequencies are defined. To verify the efficiency of the proposed LC oscillators, an experimental study is performed in the frequency range from 100 kHz to 10 MHz. The CFOAs AD844A with an external terminal z of the internal current conveyor are used as active elements. The obtained experimental results well match the results of the simulation modelling and the parameters based on the derived analytical expressions. The developed LC oscillators are intended to be used in schematic configurations of gas sensors based on surface acoustic wave (SAW) resonators.

Electronically Tunable Differential Difference Current Conveyor Using Commercially Available OTAS

This paper presents a new electronically tunable differential difference current conveyor (EDDCC) using the commercially available operational transconductance amplifiers (OTAs). Unlike the conventional DDCC, the proposed EDDCC offers current gain that can be electronically controlled. The EDDCC can be used to realize a new electronically tunable fully differential difference second-generation current conveyor (EFDCCII). Therefore, the current gain of the proposed EFDCCII can be electronically controlled. To show the advantages of the proposed EDDCC and EFDCCII, the EDDCC has been used to realize a quadrature oscillator and the EFDCCII has been used to realize a current-mode universal filter. The proposed circuits have been investigated by simulation and experimental tests using the commercially available LM13700 OTAs.

CMOS compatible sinusoidal oscillator structures with explicit voltage and current outputs

ABSTRACT The paper presents two novel circuits of sinusoidal oscillator featuring single differential difference dual-X second-generation current conveyor (DD-DXCCII) based realisation. One of the presented circuits provides voltage output signal and employs one DD-DXCCII, two capacitors and two resistors. Another presented circuit offers current output signal and employs one DD-DXCCII, two capacitors and three resistors. Both the circuits use grounded capacitors only. The output signals of presented circuits are obtainable at suitable impedance terminals (voltage signal at low impedance terminal and current signal at high impedance terminal), therefore the presented oscillator circuits offer rich cascadability. The additional performance features such as good operating frequency (49 MHz), low total harmonic distortion (<1.16%) and low power consumption (2.5 mW) are available from the presented oscillator circuits. The non-ideal, parasitic and stability aspects of the circuits are also investigated. Furthermore, the proposed ideas are enriched by presenting their MOS-C equivalent structures. Thus proposed structures are well-liked CMOS compatible structures which are well-suited to IC implementation. The presented circuits are verified through simulation outcomes which are carried out using PSPICE tool with 0.18 μm technology parameters.

A novel second generation current conveyor (CCII)-based high frequency memristor model

In this research article, we propose a combination of the second-generation current conveyor (CCII) and a PMOS circuit, emulating a memristive behavior. The voltage across the capacitor controls the conductivity of the PMOS, thus creating a non-linear conductance, also known as memductance. The maximum operating frequency is 40 MHz, the transistor count is 10 and the total power consumption of the circuit is 2.6 mW. A reduction in the transistor count by almost 40% has been achieved with this emulator circuit. When compared with the design that uses CCII the drop in the transistor count is even more i.e, by 58% approx. The proposed design has been laid using the cadence environment 180 nm process parameter and the layout occupies an area of 619.25 μm2. The theoretical analyses and simulations have been experimentally verified using CD-4007 CMOS integrated circuit (IC). Besides, a read-write operation using the proposed emulator has been included briefly. Furthermore, the current mode circuits owing to their various advantages such as less power consumption and smaller chip area pave the path for fabrication using standard CMOS technologies.

A current mode instrumentation amplifier with high common-mode rejection ratio designed using a novel fully differential second-generation current conveyor

This study presents a high common-mode rejection ratio (CMRR), and high power-supply rejection ratio (PSRR) current-mode instrumentation amplifier (CMIA) to overcome the limitations of existing differential voltage second-generation current conveyors (DVCCII)-based CMIAs in achieving high CMRR. The design is based on a fully differential second-generation current conveyor block with a novel circuit design following by a current subtracting stage. The CMIA is designed and laid out in 130 nm CMOS technology operating under ± 1.2 V supply voltage in Cadence software. The post-layout simulation results show that the CMIA achieves low-frequency voltage and current CMRR- BW of 228.8 dB–10 kHz and 246 dB–10.6 kHz, respectively, with PSRR + /PSRR- of 108.2 dB/99.7 dB, power consumption of 507 µW, and a core area of 0.0015 mm2. The unique quality of the circuit is that, it does not need well-matched active blocks, but inherently improves CMRR, bandwidth, and PSRR; hence it gains an excellent choice for integration.

An optimal design of current conveyors using a hybrid-based metaheuristic algorithm

&lt;span lang="EN-US"&gt;This paper focuses on the optimal sizing of a positive second-generation current conveyor (CCII+), employing a hybrid algorithm named DE-ACO, which is derived from the combination of differential evolution (DE) and ant colony optimization (ACO) algorithms. The basic idea of this hybridization is to apply the DE algorithm for the ACO algorithm’s initialization stage. Benchmark test functions were used to evaluate the proposed algorithm’s performance regarding the quality of the optimal solution, robustness, and computation time. Furthermore, the DE-ACO has been applied to optimize the CCII+ performances. SPICE simulation is utilized to validate the achieved results, and a comparison with the standard DE and ACO algorithms is reported. The results highlight that DE-ACO outperforms both ACO and DE.&lt;/span&gt;

CCII-Based Lossless Floating Frequency-Dependent Negative Resistor with Minimum Passive Elements

This paper proposes a new lossless floating frequency-dependent negative resistor (FDNR). The proposed floating FDNR circuit is designed with two dual output second-generation current conveyors (DO-CCIIs) and a minimum number of passive elements. The first DO-CCII behaves like a minus-type second-generation current conveyor, while the other is modified DO-CCII. The proposed floating FDNR does not require any passive element matching conditions, but all the passive elements are floating. The simulations are made through the SPICE program. A second-order high-pass filter (HPF) is given as an application example. In addition, some experimental results are included for the second-order HPF in which AD844s are utilized.

MOSFET-C Shadow Filters Based on FDCCII for Cognitive Communications

In cognitive communications, it is very important to be able to use data in different standards with a single receiver for reducing the cost. In order to achieve this, the application of shadow filters in cognitive communications provides an advantage in terms of having both a wide frequency range and an easy reconfiguration. In this paper, new MOSFET-C shadow filters based on the Fully Differential Second-Generation Current Conveyor (FDCCII) are proposed for cognitive communications. To facilitate electronic tuning of the filter parameters, MOSFET-C-based implementation is used. Fully differential applications increase the dynamic range of analog blocks. Also, fully differential implementations with MOSFET-C filters are useful in analog signal processing. The presented filters have the least number of components and no additional summing circuit. This study presents new FDCCII-based MOSFET-C shadow filters for cognitive communications design that provide HP, LP and BP transfer functions at the same time. In this study, two MOSFET-C shadow filters based on FDCCII are designed for single gain and double gain. The presented filters offer circuit simplicity compared to past shadow filter designs. The features of these new shadow filters are explained. Simulation results are presented to confirm the theoretical analysis.

Single MEXCCII-Based Grounded Immittance Functions Simulation and Applications

A simple circuit based on modified extra-X second-generation current conveyor (MEXCCII), which is capable of realizing the following grounded immittance functions: a lossless capacitor, a lossy capacitor, a lossy inductor and a lossy frequency-dependent negative conductance, is introduced in this paper. The circuit employs one MEXCCII and three passive components. The use of single active block makes the circuit structure simpler. No component’s matching constraint is needed in the proposed circuit. The nonideal study of the proposed grounded immittance circuit is also included. The circuit’s performance is examined using 0.18-[Formula: see text]m technology-based PSPICE simulations. Experimental results which are performed using off-the-shelf integrated circuits (ICs) and bread board are also included. The proposed circuit is negligibly affected by the temperature variation and process variation. A single pole high-pass filter as an application of the realized lossy capacitor and a band-pass filter as an application of the realized lossy inductor are also presented in this paper. The realized filters offer the feature of ease of cascadability.

Development of Two-Stage Quartz-Crystal Oscillators Using Monolithic Four-Terminal CFOAs

In this article, based on the well-known circuits of two-stage quartz-crystal oscillators, three electronic circuits with a small number of external components are presented. For the proposed circuit configurations, the active elements are composed of monolithic current-feedback operational amplifiers (CFOAs) with access to terminal z, between the first stage (positive second-generation current conveyor (CCII)) and the second stage (output buffer). In this way, the output signal for the developed circuits is obtained after the output buffer of the second CFOA, thereby providing a minimal effect on the resonant circuit of the oscillators. Based on a theoretical analysis of the operational principle for the proposed circuits, the linear characteristic equations and the related self-oscillation conditions are obtained. Moreover, the frequency stability coefficients are determined, which can be obtained with larger values compared to the coefficients of the known discrete transistor circuits. To verify the operability and efficiency of the proposed oscillator circuits, experimental results obtained from sample electronic circuits are presented, which confirm the analyses performed in the frequency range up to about 10 MHz.

CMOS Compatible First-Order Current Mode Universal Filter Structure and its Possible Tunable Variant

A novel first-order universal filter structure supporting current mode operation is proposed in this paper. The filter has a single active building block based realization and utilizes an extra-X second-generation current conveyor as an active building block. Additionally, the proposed circuit employs a grounded resistor and a grounded capacitor as passive components. The circuit has the ability to deliver the all-pass, high-pass, and low-pass functionalities simultaneously without meeting any passive components matching constraint. High output impedance and load insensitive outputs are other remarkable signal processing features offered by the proposed filter structure. Theoretical behavior of the proposed filter is described by presenting ideal, non-ideal, parasitic, and stability analyses. Additionally, the resistorless variant of the proposed filter is also shown to impart the tunability feature. Personal simulation program with integrated circuit emphasis (PSPICE) simulation results are presented to verify the theoretically described performance of the proposed universal filter. Complementary metal oxide semiconductor (CMOS) realization of extra-X second-generation current conveyor is utilized for the purpose of simulations, therefore, the filter is CMOS compatible.

A Review on VCII Applications in Signal Conditioning for Sensors and Bioelectrical Signals: New Opportunities.

This study reviews second-generation voltage conveyor (VCII)-based read-out circuits for sensors and bioelectrical signal conditioning from existing literature. VCII is the dual circuit of a second-generation current conveyor (CCII), which provides the possibility of processing signals in the current domain while providing output signals in the voltage form. The scope of this paper is to discuss the benefits and opportunities of new VCII-based read-out circuits over traditional ones and bioelectrical signals. The achieved main benefits compared to conventional circuits are the simpler read-out circuits, producing an output signal in a voltage form that can be directly used, improved accuracy, possibility of gain adjustment using a single grounded resistor, and the possibility of connecting several SiPM sensors to the readout circuit. The circuits studied in this paper include VCII- based read-out circuits suitable for all types of sensors configured in the current-mode Wheatstone bridge (CMWB) topology, the VCII-based read-out circuits solutions reported for silicon photomultiplier, spiral-shaped ultrasonic PVDF and differential capacitive sensors, and, finally, a simple readout circuitry for sensing bioelectrical signals. There are still not many VCII-based readout circuits, and we hope that the outcome of this study will enhance this area of research and inspire new ideas.

Improved Current Mode Biquadratic Shadow Universal Filte

In this paper, an improved single-input-multiple-output (SIMO) current-mode biquadratic shadow universal filter (SUF) is realized using two new variants of second-generation current conveyors (CCIIs), namely current conveyor cascaded transconductance amplifier (CCCTA) and extra-X current controlled conveyor transconductance amplifier (EX-CCCTA). The low pass and the band pass outputs of a non-shadow universal filter (NSUF), consisting of CCCTA, are utilized through two amplifiers' feedback paths using one EX-CCCTA to realize the proposed SUF. It is resistorless and uses two grounded capacitors only. All the five standard responses of SUF, such as low pass (LP), high pass (HP), band pass (BP), band-reject (BR), and all pass (AP), are obtained through the proposed circuit simultaneously. The important achievement of SUF over the NSUF is the ease of orthogonal tuning of the pole frequency (w o ) and quality factor (Q o ) with the bias current of CCCTA and EX-CCCTA. It is suitable for full cascadability because of proper input and output impedances. Moreover, it eases the integrated circuit implementation because of all grounded capacitors and no resistor. It does not possess any component matching constraints and consumes only 3.73mW power. The theoretical results have been validated through 180nm technology in Cadence Virtuoso.