Scan Chain Research Articles

Investigating The Clinical Manifestations, Severity And Outcomes Of COVID-19 Among Inpatients With Rheumatic Diseases: A Retrospective Cross-Sectional Study In Iran

Introduction — Patients with rheumatic diseases (RD) may be at an increased risk of developing severe symptoms of COVID-19. They are likely to have a wide range of manifestations and outcomes that can make it difficult to control the disease. The goal of this study was to investigate the clinical manifestations, severity, and outcomes of adult patients with RD hospitalized for COVID-19. Methods — We conducted a retrospective cross-sectional study. Eligible rheumatology patients were confirmed by a rheumatologist in compliance with American College of Rheumatology (ACR) criteria and had COVID-19 confirmed by computed tomography (CT) scan or polymerase chain reaction (PCR) test. Information about their gender, age, and clinical manifestations of COVID-19, along with the variables pertaining to the outcomes of the patients, was collected. Descriptive statistics and Fisher’s exact test were performed using IBM SPSS Statistics software. Results — A total of 105 patients with RD and COVID-19 were included. Rheumatoid arthritis (RA) was the most common disease (86 patients). Most patients were female (75.2%). The mean age of the participants was 58.97±12.25 years. Myalgia/arthralgia was the predominant symptom of COVID-19 (77.1%), followed by shortness of breath, cough, and fever. Only platelet count exhibited a significant association with the type of RD (p = 0.004). Conclusion — Common adverse outcomes included moderate severity based on CT grading, anemia, oxygen saturation levels (SpO2) below 90%, and severe CT-based grade of severity. The mortality rate was relatively high.

Familial Hypokalemic Periodic Paralysis Attack Following SARS‑Cov‑2 Infection: A Case Report

Familial hypokalemic periodic paralysis is a rare disorder that manifests manifests with the sudden onset of flaccid paralysis that is triggered by low levels of blood potassium, which can be caused by various factors such as, rest after intense exercise, or high-carbohydrate foods. This report presents cases of hypokalemic periodic paralysis attack triggered by severe acute respiratory syndrome coronavirus 2 (SARS-CoV-2) infection. A 29-year-old male patient was admitted with quadriparesis, fever, shortness of breath, and sever hypokalemia. The patient had a history of three episodes of Familial hypokalemic periodic paralysis (HPP). Diagnostic tests, such as chest computed tomography scan and polymerase chain reaction test, confirmed SARS-CoV-2 infection. The patient was treated with potassium chloride infusion, spironolactone, and remdesivir, and was eventually discharged from the hospital.in conclusion, SARS-CoV-2 infection can potentially exacerbate HPP and should be considered a risk factor for its occurrence.

Two-dimensional Search Space for Extracting Broadside Tests from Functional Test Sequences

Testing for delay faults after chip manufacturing is critical to correct chip operation. Tests for delay faults are applied using scan chains that provide access to internal memory elements. As a result, a circuit may operate under non-functional operation conditions during test application. This may lead to overtesting. The extraction of broadside tests from functional test sequences ensures that the tests create functional operation conditions. When N functional test sequences of length L +1 are available, the number of broadside tests that can be extracted is N · L . Depending on the source of the functional test sequences, the value of N · L may be large. In this case, it is important to select a subset of n ≤ N sequences and consider only the first l ≤ L clock cycles of every sequence for the extraction of n · l ≪ N · L broadside tests. The two-dimensional N × L search space for broadside tests is the subject of this article. Using a static procedure that considers fixed values of N and l , the article demonstrates that, for the same value of N · L , different circuits benefit from different values of N and l . It also describes a dynamic procedure that matches the parameters N and l to the circuit. The discussion is supported by experimental results for transition faults in benchmark circuits.

A new die-level flexible design-for-test architecture for 3D stacked ICs

A die-level design-for-test architecture for 3D stacked ICs is proposed. The main component of this architecture is a newly proposed configurable boundary cell, based on which flexible parallel test is achieved. Both of the number of parallel scan chains and their lengths can be configured during test. This test architecture features light-weight, high flexibility in parallel test configuration, modularity, and IEEE P1149.1 compatibility. In this work, both infrastructure and implementation aspects are illustrated. Experimental results demonstrate desired test acceleration. The acceleration ratio approximately reaches its limit, which equals the number of parallel scan chains, when the number of test vectors is over 300.

A dependable and resource-frugal ring oscillator physically unclonable function

ABSTRACT Silicon Physical Unclonable Function (PUF) is a crucial component for hardware security, providing unique device identification in networks. PUF provides robust security for cryptographic keys and IC digital fingerprints. However, resource constraints in network devices limit its use in security protocols. To address this challenge, PUF offers a lightweight hardware security solution with two main types: strong PUF (e.g. arbiter PUF) and Ring Oscillator (RO) PUF. The first option produces large CRPs with improved security but incurs hardware overhead, whereas the second option offers lower overhead with smaller CRP size, leading to reduced security. This paper introduces a novel, cost-effective solution to enhance RO PUF security while reducing hardware limitations. Our proposal involves a resource sharing technique with scan flip-flops, multiplexers, and inverter logic. This approach takes advantage of existing scan chains in circuit netlists to reduce PUF area without sacrificing uniqueness. A specific set of test patterns and odd number of inverters transform the memory-based PUF into an RO PUF. Our solution also leverages pass transistor-based implementation to significantly reduce power consumption and area overhead. Simulation results show that our approach effectively reduces area and power consumption while maintaining PUF uniqueness.

A secure scan architecture using dynamic key to thwart scan-based side-channel attacks

Scan testing is widely used in the rigorous testing of modern integrated circuits. However, the controllable and observable nature of the scan design also provides opportunities for attackers who can utilise this structure to steal secret information stored in the chip. This paper proposes a secure Design for Testability (DFT) architecture to prevent scan-based attacks. The scheme uses a modified Linear Feedback Shift Register (LFSR) to dynamically generate keys for the scan design key generator and verifies them against a specific selection of test key flip-flops in the original scan chain, and locks the control signals by transmitting the outputs of the verification comparisons to a OR gate. When the test authorisation key is correct, the circuit performs a normal scan operation; otherwise, the circuit enters an abnormal test mode and the data in the scan chain is dynamically obfuscated, thus preventing from observing valid data or deriving an encryption key through the output of the scan chain.

Developments in scan shift power reduction: a survey

While power reduction during testing is necessary for today's low-power devices, it also lowers test costs. Scan-based methods are the most widely used approach for testing integrated circuits (IC). Test vectors are shifted into and out of scan chains bit by bit during shift operation. The time required for shift operation dominates the test time. With the geometries shrinking (7 nm→5 nm→3 nm→1.8 nm), ICs are required to be tested for newer defects, increasing test time. The most effective way to reduce test time for scan operation is to increase the frequency of the shift operation. Reduction in shift power enables scan operation to be performed with increased frequency, reducing test time, and test cost. This paper presents a survey of techniques proposed recently for shift power reduction. Various techniques, including special flip-flop usage, segmentation, reordering, and low-pass filter, are being reviewed. The techniques are organized based on main attributes to underscore their similarities and differences. Pros and cons in terms of complexities involved in their implementation are discussed. We believe this paper will provide a point of reference for further studies in scan shift power reduction and will be helpful to both industry and academia.

Design of a Scan Chain for Side Channel Attacks on AES Cryptosystem for Improved Security

Scan chain-based attacks are side-channel attacks focusing on one of the most significant features of hardware test circuitry. A technique called Design for Testability (DfT) involves integrating certain testability components into a hardware design. However, this creates a side channel for cryptanalysis, providing crypto devices vulnerable to scan-based attacks. Advanced Encryption Standard (AES) has been proven as the most powerful and secure symmetric encryption algorithm announced by USA Government and it outperforms all other existing cryptographic algorithms. Furthermore, the on-chip implementation of private key algorithms like AES has faced scan-based side-channel attacks. With the aim of protecting the data for secure communication, a new hybrid pipelined AES algorithm with enhanced security features is implemented. This paper proposes testing an AES core with unpredictable response compaction and bit level-masking throughout the scan chain process. A bit-level scan flipflop focused on masking as a scan protection solution for secure testing. The experimental results show that the best security is provided by the randomized addition of masked scan flipflop through the scan chain and also provides minimal design difficulty and power expansion overhead with some negligible delay measures. Thus, the proposed technique outperforms the state-of-the-art LUT-based S-box and the composite sub-byte transformation model regarding throughput rate 2 times and 15 times respectively. And security measured in the avalanche effect for the sub-pipelined model has been increased up to 95 per cent with reduced computational complexity. Also, the proposed sub-pipelined S-box utilizing a composite field arithmetic scheme achieves 7 per cent area effectiveness and 2.5 times the hardware complexity compared to the LUT-based model.

ASIC Implementation for Multiple Scan at Register Transfer Level

Design for testability (DFT) is introduced to reduce the complexity of testing integrated circuit and help improve fault coverage. However, conventional DFT with additional 2-to-1 multiplexer (MUX) might add an increasing amount of delay and area overhead. Therefore, register transfer level (RTL) scan design is introduced to overcome this problem. This paper aims to present the development of an ASIC with RTL scan design by using multiple scan paths instead of the conventional technique, which is gate-level (GL) scan insertion to insert scan cells. This method inserts multiple scan cells by utilizing the existing multiplexer and operational units in order to reduce area overhead and delay. Besides, multiple scan paths are implemented instead of a single scan chain to reduce the complexity of the testing process, where a single scan chain has long test application times due to the high number of clock cycles for the scan chain process. RTL design is also modified by adding an extra gate for multiple scan chain insertion. The graph is derived in order to analyse the connection between registers such that the multiple scan paths can be determined accordingly. Synopsys tool is used for synthesized, placement and routing and performing automatic test pattern generation while static timing analysis is used to verify the results of the setup slack time for ASIC design. The simulation result shows that multiple scan paths insertion at RTL level has an area overhead and slack time of about 3.79% and 0.44ns less compared to multiple scan paths insertion at GL for a finite impulse response circuit with comparable high fault coverage and small delay. A comparison of the performance metrics such as area, setup slack time, and fault coverage of the multiple scan chain is done between the RTL scan and GL scan.

GPU-Accelerated Estimation and Targeted Reduction of Peak IR-Drop during Scan Chain Shifting

GPU-Accelerated Estimation and Targeted Reduction of Peak IR-Drop during Scan Chain Shifting

STRAIT: Self-Test and Self-Recovery for AI Accelerator

As the demand for data-intensive analytics has increased with the rapid advance in artificial intelligence (AI), various AI accelerators have been proposed. However, as AI-based solutions have been adapted to applications requiring accuracy and reliability, the reliability of them has become a critical issue. For this reason, self-test and self-recovery for AI accelerator (STRAIT) is proposed in this paper. It facilitates self-test, self-diagnosis, and self-recovery by utilizing the structural and operational characteristics of systolic array in AI accelerator. The proposed self-test is progressed using scan chains composed of functional paths, and can achieve a 100% test coverage (for both stuck-at and transition-delay faults) with small number of test patterns and reduced test power. The proposed self-diagnosis is progressed with the proposed self-test in real-time, and allows accurate fault localization with fault type analysis. The proposed self-recovery is progressed using efficient pruning for faulty processing elements with weight allocation, and the reliability of AI accelerators can drastically increase with negligible performance degradation. However, STRAIT can be implemented with a small area overhead.

Cluster-based test vector re-ordering for reduced power dissipation in digital circuits

Optimizing testing power is a paramount concern in modern digital circuit design, particularly as the intricacy of circuits continues to rise. This issue becomes even more pronounced with the scaling down of feature sizes due to advancements in process technology. The increase in testing power dissipation, beyond the regular operational state, raises red flags for both designers and test engineers. This paper introduces a novel cluster-based approach, shedding light on the efficient reordering of test vectors to mitigate the heightened switching activity. This technique aims to reduce the power consumption during testing, while still ensuring efficient error detection, maintaining the test period, and preserving the original order of the scan chain. Importantly, this reordering method does not introduce any additional area or test time overhead, minimizing the risks associated with these factors. The potential impact of this approach is demonstrated through concrete examples drawn from ISCAS’89 benchmark circuits. The results showcase a notable 11% reduction in switching activity, all while preserving fault coverage levels.

Scan Chain Architecture With Data Duplication for Multiple Scan Cell Fault Diagnosis

Scan chain diagnosis is an important step in solving yield problems in early manufacturing processes. The higher the diagnostic resolution, the better the yield in the initial process. In the conventional scan chain architecture, if failed scan chain data are observed during scan mode, all the shifted data through a stuck-at faulty cell are contaminated. As a result, only a single fault can be diagnosed, and there are difficulties in diagnosing multiple stuck-at fault locations. The number of multiple faults has increased significantly, increasing the cost of physical fault analysis. In addition, it is difficult to diagnose faults with a high resolution because there are many candidate faults early in the process. In this paper, a new hardware architecture with data duplication is proposed to diagnose fault locations by deliberate voltage collision even if multiple faults occur. The resources required for the diagnosis include a minimum of one good scan chain, a diagnosis circuit, and a diagnostic line. Experimental results show that the proposed method has lower hardware and routing overhead and fewer additional pin counts than the existing method. The diagnostic speed is also faster, and the larger the number of scan chains (the larger the circuit), the higher the diagnostic performance, which has advantages over conventional methods.

An IEEE-Compatible JTAG Test-Access-Port Controller for RSFQ Logic and Systems

JTAG, an IEEE-standard test protocol, is widely used for testing commercial and experimental CMOS chips but appears unused for testing superconducting chips. The test-access-port (TAP) controller described here facilitates the use of JTAG to reduce the cost – in time and effort – of testing superconductive circuits. Our RSFQ-based TAP controller shifts data serially through a scan chain that transfers data in parallel to and from a circuit under test. Suitably designed scan chains can provide initial values to superconducting circuits and retrieve results to explore circuit behavior. A control computer or an internet connection can operate our TAP controller through a simple five-wire interface. Our TAP controller implements the TAP part of IEEE standard 1149.8.1-2012 in an area of only 580 x 280 micrometers, less area than two bonding pads. Our TAP Controller design information and MIT SFQ5ee layout will be freely available.

Prevalence and complication of COVID-19 in patients with ankylosing spondylitis (AS) and its relationship with TNF-a inhibitors.

Ankylosing spondylitis (AS) is a condition that is treated with nonsteroidal anti-inflammatory drugs and biological drugs such as anti tumor necrosis factor alpha (TNF-α). This study examined the prevalence of COVID-19 among individuals with AS and compare it between those receiving and not receiving TNF-α inhibitors. A cross-sectional study was conducted at the rheumatology clinic of Imam Khomeini Hospital in Tehran, Iran. The study included patients with AS who sought treatment at the clinic. Demographic information, laboratory and radiographic findings, and disease activity were recorded through interviews and examinations using a questionnaire. A total of 40 patients were studied over the course of 1 year. Among them, 31 patients were administered anti-TNF-α drugs, with 15 patients (48.3%) receiving subcutaneous Altebrel (Etanercept), 3 patients (9.6%) receiving intravenous Infliximab, and 13 patients (41.9%) receiving subcutaneous Cinnora (Adalimumab). Of the total, 7 patients (17.5%) tested positive for COVID-19, 1 of whom was confirmed through both CT scan and polymerase chain reaction (PCR) testing, while the remaining 6 patients were confirmed only through PCR testing. All patients tested positive for COVID-19 were male, and 6 of them had received Altebrel. Among the 9 AS patients who did not receive TNF inhibitors, 1 patient contracted SARS-CoV-2. The clinical symptoms experienced by these patients were mild, and hospitalization was not required. However, 1 patient who had insulin-dependent type 1 diabetes and was receiving Infliximab required hospitalization. This patient exhibited more severe COVID-19 symptoms, including high fever, pulmonary involvement, dyspnea, and decreased oxygen saturation. No cases of COVID-19 were reported in the Cinnora treatment group. The use of any of the drugs did not demonstrate a significant relationship with the occurrence of COVID-19 in patients. The use of the TNF-α inhibitors in patients with AS, may be associated with reduced hospitalization and death rate in COVID-19 cases.

New Approaches of Side-Channel Attacks Based on Chip Testing Methods

The state-of-the-art test infrastructure security is based on the assumption of preventing access to the sensitive information and the (publicly) accessible outputs or test infrastructure subset are supposed to not leak any secret information. In addition, for achieving functional safety requirements, the on-chip test infrastructure is re-used in-field and cannot be completely disabled after manufacturing test phase. Therefore, the access to the scan chains or similar test access ports which can lead to sensitive information needs to be restricted or encrypted to guarantee the security of the test infrastructure. However, in this work we show that having access to (small delay) test results on insensitive (public) outputs can in fact reveal secret data. Using real hardware, we have performed template attacks using the results of delay testing on the output of cryptographic circuits and were able to retrieve the key with very few test inputs. This template attack requires only a few random patterns on the victim device, which could be different from the device used for template building. In addition, the attack is also resilient against runtime variation and noise, as well as inaccuracies and down-sampling of delay testing measurements.

A 14-year-old boy with multiple trauma and bilateral basal ganglia hemorrhage due to coronavirus disease 2019: a case report

BackgroundIn December 2019, coronavirus disease 2019 spread worldwide, causing acute respiratory distress syndrome. Coronavirus disease 2019 presents from an asymptomatic infection to severe disease causing multiorgan failure. Neurological manifestations were observed in some patients, including intracerebral hemorrhage. Bilateral basal ganglia hemorrhage is rare due to trauma.Case presentationOur patient was a 14-year-old Iranian boy with multiple trauma and loss of consciousness who tested positive for coronavirus disease 2019. The brain computed tomography scan reported bilateral basal ganglia hemorrhage. Bilateral ground glass opacity was reported through a chest computed tomography scan.Discussion and conclusionsIn this study, we reported a 14-year-old boy referred to the emergency room due to multiple trauma. Through the medical interventions, bilateral basal ganglia hemorrhage was discovered incidentally. Coronavirus disease 2019 was detected in this patient on the basis of findings in chest computed tomography scan and positive real reverse transcription polymerase chain reaction test. Several clinical reports and series exploring the relationship between coronavirus disease 2019 and ischemic strokes have been published. Coronavirus disease 2019, like other acute respiratory syndromes, can invade the central nervous system through hematogenous and neuronal dissemination or it can be an immune response to the cytokine storm. In conclusion, it is vital to know the pathophysiology of the neurological manifestations of coronavirus disease 2019 and prevent the mild neurological manifestations leading to severe conditions.

A Novel Secure Scan Design Based on Delayed Physical Unclonable Function

The advanced integrated circuits have been widely used in various situations including the Internet of Things, wireless communication, etc. But its manufacturing process exists unreliability, so cryptographic chips must be rigorously tested. Due to scan testing provides high test coverage, it is applied to the testing of cryptographic integrated circuits. However, while providing good controllability and observability, it also provides attackers with a backdoor to steal keys. In the text, a novel protection scheme is put forward to resist scan-based attacks, in which we first use the responses generated by a strong physical unclonable function circuit to solidify fuse-antifuse structures in a non-linear shift register (NLSR), then determine the scan input code according to the configuration of the fuse-antifuse structures and the styles of connection between the NLSR cells and the scan cells. If the key is right, the chip can be tested normally; otherwise, the data in the scan chain cannot be propagated normally, it is also impossible for illegal users to derive the desired scan data. The proposed technique not only enhances the security of cryptographic chips, but also incurs acceptable overhead.

Novel Double Modular Redundancy Based Fault-Tolerant FIR Filter for Image Denoising

In signal processing and communication systems, digital filters are widely employed. In some circumstances, the reliability of those systems is crucial, necessitating the use of fault tolerant filter implementations. Many strategies have been presented throughout the years to achieve fault tolerance by utilising the structure and properties of the filters. As technology advances, more complicated systems with several filters become possible. Some of the filters in those complicated systems frequently function in parallel, for example, by applying the same filter to various input signals. Recently, a simple strategy for achieving fault tolerance that takes advantage of the availability of parallel filters was given. Many fault-tolerant ways that take advantage of the filter’s structure and properties have been proposed throughout the years. The primary idea is to use structured authentication scan chains to study the internal states of finite impulse response (FIR) components in order to detect and recover the exact state of faulty modules through the state of non-faulty modules. Finally, a simple solution of Double modular redundancy (DMR) based fault tolerance was developed that takes advantage of the availability of parallel filters for image denoising. This approach is expanded in this short to display how parallel filters can be protected using error correction codes (ECCs) in which each filter is comparable to a bit in a standard ECC. “Advanced error recovery for parallel systems,” the suggested technique, can find and eliminate hidden defects in FIR modules, and also restore the system from multiple failures impacting two FIR modules. From the implementation, Xilinx ISE 14.7 was found to have given significant error reduction capability in the fault calculations and reduction in the area which reduces the cost of implementation. Faults were introduced in all the outputs of the functional filters and found that the fault in every output is corrected.

A Hybrid Test Scheme for Automotive IC in Multisite Testing

This article proposes a hybrid test scheme based on interleaved test applications to increase the efficiency of multisite testing of integrated circuits (ICs) by solving problems related to test coverage, which is an important feature in automotive IC, and test costs, including the number of test pins and the volume of test data. To solve the problems, a hybrid test scheme that combines the merits of broadcast-based scan compression and built-in self-test (BIST) is proposed. The proposed scheme not only generates deterministic test patterns, similar to scan compression, but also requires fewer test pins, similar to BIST, thereby increasing the efficiency of multisite testing. With appropriately designed linear-feedback shift registers (LFSRs) and seeds periodically inserted through the reduced test pins, the test application process combines deterministic testing and random testing. The random testing stage can compensate the seed-insertion time for the subsequent deterministic testing stage and reduce the number of required deterministic patterns by detecting easy-to-detect faults. For further reduction of the volume of test data and hardware overhead, some compatible scan chains (SCs) are grouped and receive test data from an LFSR. The experimental results show that the proposed method increases the efficiency of multisite testing with a reduced pin count.