Scan Chain Input Research Articles

Extended Transparent-Scan

Transparent-scan is an approach to test compaction where scan shift cycles and functional capture cycles are interleaved in arbitrary ways as needed for detecting target faults. This is achieved by viewing the scan enable input as a regular primary input that can be assigned arbitrary sequences of zero and one values. This paper notes that transparent-scan leaves an unused combination of the scan enable and scan chain input values. This paper suggests that the unused combination can control design-for-testability logic to achieve better test compaction. At the cost of one additional EXCLUSIVE-OR gate for every state variable, and routing of the scan chain input to all the flip-flops, the extended transparent-scan approach described in this paper allows the values of the next-state variables to be complemented before they are latched in the flip-flops during a functional capture cycle. Extended transparent-scan is developed under bounded transparent-scan, where scan-in and scan-out operations of a conventional scan-based test set are maintained in order to limit the computational cost. Experimental results for transition faults in the functional logic of benchmark circuits demonstrate the additional test compaction that can be achieved with extended transparent-scan. Transition faults in the scan logic are considered as well.

Energy-Efficient Scheme for Multiple Scan-Chains BIST Using Weight-Based Segmentation

This brief presents a weighted-based cell segmentation algorithm for a multiple scan-chains built-in self-test in order to reduce the average power consumption when scanning new test vectors and to reduce the test application time. The proposed technique is based on selecting the best group of cells to be connected in the same scan-chain. This group of cells should have the same or very close weight of logic 1s and 0s, which will be optimal to get the highest fault coverage in a specified test length. Then each scan-chain input will be connected to an output of a combinational circuit located after the linear feedback shift register that will generate biased test vectors according to the optimal weight of this segment of cells in the scan-chain. Thus, increasing the fault coverage and smoothing the applied test patterns which will reduce the power consumption. Experimental results on ISCAS’89 benchmark circuits show that using the proposed design can save on average about 35.75% of the test application time, 30.95% of the average power consumption, which means huge energy saving with an average of 55.6% for 20 ISCAS’89 benchmark circuits.

IJARCCE - Computer and Communication Engineering

An arbitrary design implemented into a field-programmable gate array (FPGA). FPGA contains many logical blocks. Fault equivalence and fault dominance method are used to detect the fault with minimum time period. An approach provides transparent scan to share tests among different logic blocks whose primary inputs and outputs are included in scan chains even if the blocks have different numbers of state variables. The transparent-scan sequences based on tests for one logic block could detect faults in other logic blocks, with different numbers of state variable. It uses n number of test configuration instead of 2 n number of test configuration by test code algorithm. Transparent scan enhances the ability to produce a compact test set for a group of logic blocks. The procedure obtains a set of transparent-scan sequences for a group of logic blocks from compacted test sets for the logic blocks in the group. From this set, it chooses a subset that finds all the target faults, which are propagated by the complete set by using Modelsim and area is obtained by using the XILINX ISE 8.1 software. An approach to test application called transparent scan, the scan-select and scan-chain inputs of a scan circuit are considered as inputs of the sequential circuit in the same way as the primary inputs, and the scan-chain outputs are considered as outputs in the same way as the primary outputs. A test sequence under transparent scan specifies the values for all the inputs without distinguishing between them based on the types. The corresponding output sequence specifies values for all the outputs, again, without distinguishing between them based on their types. Faults are allowed to be detected during all the clock cycles of a transparent-scan sequence. In general, fault coverage is computed by sequential fault simulation of the transparent-scan sequence. This view of the test

Reducing Test Power and Improving Test Effectiveness for Logic BIST

Excessive power dissipation is one of the major issues in the testing of VLSI systems. Many techniques are proposed for scan test, but there are not so many for logic BIST because of its unmanageable randomness. This paper presents a novel low switching activity BIST scheme that reduces toggle frequency in the majority of scan chain inputs while allowing a small portion of scan chains to receive pseudorandom test data. Reducing toggle frequency in the scan chain inputs can reduce test power but may result in fault coverage loss. Allowing a small portion of scan chains to receive pseudorandom test data can make better uniform distribution of 0 and 1 and improve test effectiveness significantly. When compared with existing methods, experimental results on larger benchmark circuits of ISCAS’89 show that the proposed strategy can not only reduce significantly switching activity in circuits under test but also achieve high fault coverage.

Reducing the input test data volume under transparent scan

Under an approach to test compaction called transparent scan, a scan circuit is considered as a sequential circuit where the scan-chain inputs and scan-select input are included in the set of inputs of the circuit. This provides the flexibility to interleave functional and scan clock cycles in arbitrary ways, and enhances the ability of transparent-scan sequences to detect target faults. These features are used in this study for reducing the input test data volume by using the same scan-chain input sequences with different scan-select sequences to define transparent-scan sequences. The circuits under consideration have a scan chain that includes their state variables, primary inputs and primary outputs. Scan-chain input sequences are computed based on a given conventional scan-based test set that includes compacted single-cycle and two-cycle test sets for single stuck-at and transition faults, respectively. The set of scan-select sequences is fixed. Using the same scan-chain input sequences for defining several transparent-scan sequences, with different scan-select sequences, allows more faults to be detected with the same set of scan-chain input sequences. This allows the number of scan-chain input sequences to be reduced compared with the number of tests in the conventional scan-based test set.

Transparent-Segmented-Scan without the Routing Overhead of Segmented-Scan

We introduce a combination of segmented-scan and transparent-scan referred to as transparent-segmented-scan. Segmented-scan is a design-for-testability approach for reducing the power dissipation of scan-based tests. Transparent-scan is a test application scheme that was proposed as a way to obtain highly compacted test sequences. The combination allows the generation of compact test sequences with reduced power dissipation. Moreover, since transparent-scan views scan shift and functional capture cycles uniformly, both scan shift and functional capture power are reduced together. We explore a particular implementation of transparent-segmented-scan that does not require the scan chain input and output to be routed to all the segments of a scan chain, as in segmented-scan. This avoids the routing overhead of segmented-scan. It is made possible by the properties of transparent-scan that also contribute to test compaction.

Bit-Swapping LFSR and Scan-Chain Ordering: A Novel Technique for Peak- and Average-Power Reduction in Scan-Based BIST

This paper presents a novel low-transition linear feedback shift register (LFSR) that is based on some new observations about the output sequence of a conventional LFSR. The proposed design, called bit-swapping LFSR (BS-LFSR), is composed of an LFSR and a 2 times 1 multiplexer. When used to generate test patterns for scan-based built-in self-tests, it reduces the number of transitions that occur at the scan-chain input during scan shift operation by 50% when compared to those patterns produced by a conventional LFSR. Hence, it reduces the overall switching activity in the circuit under test during test applications. The BS-LFSR is combined with a scan-chain-ordering algorithm that orders the cells in a way that reduces the average and peak power (scan and capture) in the test cycle or while scanning out a response to a signature analyzer. These techniques have a substantial effect on average- and peak-power reductions with negligible effect on fault coverage or test application time. Experimental results on ISCAS'89 benchmark circuits show up to 65% and 55% reductions in average and peak power, respectively.

Survey of Scan Chain Diagnosis

Scan-based testing has proven to be a cost-effective method for achieving good test coverage in digital circuits. The Achilles heel in the application of scan-based testing is the integrity of the scan chains. The amount of die area consumed by scan elements, chain connections, and control circuitry varies with different designs. Typically, each scan cell in a scan chain has an index number. The cells in the chain are sequentially numbered from scan output to scan input, starting with 0. A chain pattern (sometimes called a flush pattern) is a pattern consisting of shift-in and shift-out operations without pulsing capture clocks. The purpose of chain patterns is to test scan chain integrity. A scan pattern (also known as a logic test pattern) is a pattern consisting of a shift-in operation, one or multiple capture clock cycles, and a shift-out operation. The purpose of scan patterns is to test system logic. The scan cells between the scan chain input and a scan cell's scan input terminal are called the upstream cells of that scan cell. The scan cells between the scan chain output and a scan cell's scan output terminal are called the downstream cells of that scan cell.

Transparent DFT: a design for testability and test generation approach for synchronous sequential circuits

This paper describes a design for testability (DFT) approach for synchronous sequential circuits that combines scan with nonscan DFT in a transparent way. DFT control inputs and scan chain inputs are used as primary inputs of the circuit, and scan chain outputs are used as primary outputs of the circuit during test generation to eliminate the distinction between functional clock cycles and the various types of nonfunctional clock cycles. The result is 1) short test application times due to the nonscan DFT modes and the ability to use limited scan operations and 2) the ability to detect all the combinationally irredundant faults due to the scan mode

Test generation for embedded circuits under the transparent-scan approach

A new test generation procedure is introduced for scan circuits under an approach called transparent-scan. The new test generation procedure targets a circuit-under-test that is embedded in a larger design (it is also applicable to an interconnection of embedded circuits). Transferring deterministic test data to the primary inputs of an embedded circuit from an external source can be expensive. This problem is alleviated as follows. The test generation procedure starts from a given input sequence Ψ that specifies the values of the original primary inputs of the circuit (the primary inputs before scan was added). In this implementation, Ψ is a random input sequence that can be generated by an on-chip test-pattern generator (e.g. a linear-feedback shift register) driving the original primary inputs of the circuit. The test generation procedure transforms Ψ into a test sequence T for the scan circuit under the transparent-scan approach by adding to Ψ the values of the scan select and scan chain inputs. These inputs are easily controllable from the primary inputs of the design.