Scan Chain Diagnosis Research Articles

Scan Chain Architecture With Data Duplication for Multiple Scan Cell Fault Diagnosis

Scan chain diagnosis is an important step in solving yield problems in early manufacturing processes. The higher the diagnostic resolution, the better the yield in the initial process. In the conventional scan chain architecture, if failed scan chain data are observed during scan mode, all the shifted data through a stuck-at faulty cell are contaminated. As a result, only a single fault can be diagnosed, and there are difficulties in diagnosing multiple stuck-at fault locations. The number of multiple faults has increased significantly, increasing the cost of physical fault analysis. In addition, it is difficult to diagnose faults with a high resolution because there are many candidate faults early in the process. In this paper, a new hardware architecture with data duplication is proposed to diagnose fault locations by deliberate voltage collision even if multiple faults occur. The resources required for the diagnosis include a minimum of one good scan chain, a diagnosis circuit, and a diagnostic line. Experimental results show that the proposed method has lower hardware and routing overhead and fewer additional pin counts than the existing method. The diagnostic speed is also faster, and the larger the number of scan chains (the larger the circuit), the higher the diagnostic performance, which has advantages over conventional methods.

Scan Cell Modification for Intra Cell-Aware Scan Chain Diagnosis

Conventional diagnosis methods are performed at the library cell level, which identify only defective cells. In reality, many defects affecting the inside of the cells cannot be identified, limiting yield improvement. To overcome the limit, cell-aware diagnosis has been introduced, but it is rarely used in scan chain domain due to the characteristics of a scan cell. Design of the scan cell is complex, but there are few I/O pins to control and observe. In this brief, the scan cell design is modified to observe more values inside the cell, distinguishing the many defect that could not be identified. Since the proposed method is not affected by logic and proceeds at the layout level of the scan cells, it is immune to type, size, or complexity of the circuit. Based on the layout data and some analog simulations, a new modified cell view for the intracell scan chain diagnosis is developed.

Reconfigurable Scan Architecture for High Diagnostic Resolution

Scan chain diagnosis is essential to solving yield-reduction problem caused by the miniaturization of manufacturing process. The accurate diagnosis of scan chain faults that frequently occur in the initial process is vital for rapidly improving yield. Moreover, the importance of scan chain diagnosis with a high resolution for the multiple faults is increasing because multiple faults occur in the early stages of the process, further increasing the cost of physical failure analysis. Although multiple faults can be diagnosed with existing methods, a high diagnostic resolution is difficult to achieve in the early stages of the process (where many faults occur) due to the rapid increase in the number of diagnosed fault candidates as the number of actual faults in the circuit increases. In this paper, a novel reconfigurable scan architecture that reconfigures the diagnosis paths and a test algorithm that uses this scan architecture are proposed to reduce the number of diagnosed fault candidates in the scan chain diagnosis with multiple circuit faults. Experimental results indicate that the proposed method achieves the higher diagnostic resolution for multiple faults than conventional methods. In addition, the proposed method reduces the routing overhead by scan partitioning.

Scan-Chain-Fault Diagnosis Using Regressions in Cryptographic Chips for Wireless Sensor Networks.

Scan structures, which are widely used in cryptographic circuits for wireless sensor networks applications, are essential for testing very-large-scale integration (VLSI) circuits. Faults in cryptographic circuits can be effectively screened out by improving testability and test coverage using a scan structure. Additionally, scan testing contributes to yield improvement by identifying fault locations. However, faults in circuits cannot be tested when a fault occurs in the scan structure. Moreover, various defects occurring early in the manufacturing process are expressed as faults of scan chains. Therefore, scan-chain diagnosis is crucial. However, it is difficult to obtain a sufficiently high diagnosis resolution and accuracy through the conventional scan-chain diagnosis. Therefore, this article proposes a novel scan-chain diagnosis method using regression and fan-in and fan-out filters that require shorter training and diagnosis times than existing scan-chain diagnoses do. The fan-in and fan-out filters, generated using a circuit logic structure, can highlight important features and remove unnecessary features from raw failure vectors, thereby converting the raw failure vectors to fan-in and fan-out vectors without compromising the diagnosis accuracy. Experimental results confirm that the proposed scan-chain-diagnosis method can efficiently provide higher resolutions and accuracies with shorter training and diagnosis times.

Improving the Diagnosability of Scan Chain Faults Under Transparent-Scan by Observation Points

Observation points in the combinational logic of a circuit can aid in the diagnosis of logic defects by reducing the number of indistinguished fault pairs. This paper considers the use of observation points in the combinational logic for the diagnosis of scan chain defects under an approach to test application called transparent-scan. Tests that are used for the diagnosis of scan chain defects include functional capture cycles that propagate the effects of scan chain faults through the combinational logic. Scan chain faults can thus be distinguished based on the values that are propagated in their presence to an observation point in the combinational logic. The procedure for observation point insertion considers the following parameters with respect to scan chain faults: 1) the number of indistinguished fault pairs and 2) the distances, measured in numbers of scan cells, between the faults that cannot be distinguished. With lower distances, a set of candidates for a faulty scan chain is likely to contain faults in the same vicinity of the scan chain. This facilitates failure analysis. Experimental results demonstrate the effectiveness of observation points in the combinational logic for scan chain diagnosis under transparent-scan.

Scan Chain Masking for Diagnosis of Multiple Chain Failures in a Space Compaction Environment

Diagnosis is extremely important to ramp up the yield during the integrated circuit manufacturing process. It reduces the time to market and product cost. Limited observability due to test response compaction negatively affects the diagnosis procedure. When multiple chains, mapped to a single compactor, fail, diagnosis becomes extremely difficult. The procedure is even more complicated because when a circuit fails the flush test, not all the patterns are applied. Only a few of the patterns are applied and the observed responses are used to diagnose the faulty chains. In this paper, we have proposed an efficient masking strategy that will be very useful for diagnosis of scan chains when multiple scan chains fail. The proposed strategy uses the redundancy in fault detection by the test patterns and masks scan chains in such a way that enough information can be provided with small increase in test pattern count. A new tester architecture that will select and apply only those patterns having enough information for diagnosis has also been proposed. Diagnostic resolution and first hit index achieved by our method are very close to their ideal values, which validate the applicability of our approach.

Utilizing Circuit Structure for Scan Chain Diagnosis

Scan chain diagnosis has become a critical issue to yield loss in modern technology. In this paper, we present a scan chain partitioning algorithm and a scan chain reordering algorithm to improve scan chain fault diagnosis resolution. In our scan chain partition algorithm, we take into consideration not only logic dependency but also the controllability between scan flip-flops. After the partition step, the ordering of scan cells is performed to decrease the range of suspect faulty scan cells by a bipartite matching reordering algorithm. The experimental results show that our method can reduce the number of suspect scan cells from 378-31 to at most 3 for most cases of ITC'99 benchmarks.

DiSC: A New Diagnosis Method for Multiple Scan Chain Failures

In scan-based testing environments, identifying the scan chain failures can be of significant help in guiding the failure analysis process for yield improvement. In this paper, we propose an efficient scan chain diagnosis method using a symbolic fault simulation to achieve high diagnostic resolution and small candidate list for single and multiple defects in scan chains. The main ideas of the proposed scan chain diagnosis method are twofold: 1) the reduction of the candidate scan cells through the analysis of the symbolic simulation responses, and 2) the identification of final candidate scan cells using the backward tracing method with the symbolic simulation responses. Experimental results show the effectiveness.

Survey of Scan Chain Diagnosis

Scan-based testing has proven to be a cost-effective method for achieving good test coverage in digital circuits. The Achilles heel in the application of scan-based testing is the integrity of the scan chains. The amount of die area consumed by scan elements, chain connections, and control circuitry varies with different designs. Typically, each scan cell in a scan chain has an index number. The cells in the chain are sequentially numbered from scan output to scan input, starting with 0. A chain pattern (sometimes called a flush pattern) is a pattern consisting of shift-in and shift-out operations without pulsing capture clocks. The purpose of chain patterns is to test scan chain integrity. A scan pattern (also known as a logic test pattern) is a pattern consisting of a shift-in operation, one or multiple capture clock cycles, and a shift-out operation. The purpose of scan patterns is to test system logic. The scan cells between the scan chain input and a scan cell's scan input terminal are called the upstream cells of that scan cell. The scan cells between the scan chain output and a scan cell's scan output terminal are called the downstream cells of that scan cell.

A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques

Scan chains are popularly used as the channels for silicon testing and debugging. However, they have also been identified as one of the culprits of silicon failure more recently. To cope with this problem, several scan chain diagnosis approaches have been proposed in the past. The existing methods, however, suffer from one common drawback—that is, they rely on fault models and matching heuristics to locate the faults. Such a paradigm may run into difficulty when the fault under diagnosis does not match the fault model exactly, for example, when there is a bridging between a flip-flop and a logic cell, or the fault is temporal and only manifests itself intermittently. In light of this, we propose in this article a more versatile model-free paradigm for locating the faulty flip-flops in a scan chain, incorporating a number of signal processing techniques, such as filtering and edge detection. These techniques performed on the test responses of the failing chip under diagnosis directly can effectively reveal the fault location(s) in a scan chain. As compared to the previous works, our approach is better capable of handling intermittent faults and bridging faults, even under nonideal conditions, for example, when the core logic is also faulty. Experimental results on several real designs indicate that this approach can indeed catch some nasty faults that previous methods could not catch.

A New Scan Chain Fault Simulation for Scan Chain Diagnosis

In this paper, we propose a new symbolic simulation for scan chain diagnosis to solve the diagnosis resolution problem. The proposed scan chain fault simulation, called the SF-simulation, is able to analyze the effects caused by faulty scan cells in good scan chains. A new scan chain fault simulation is performed with a modified logic ATPG pattern. In this simulation, we consider the effect of errors caused by scan shifting in the faulty scan chain. Therefore, for scan chain diagnosis, we use the faulty information in good scan chains which are not contaminated by the faults while unloading scan out responses. The SF-simulation can tighten the size of the candidate list and achieve a high diagnosis resolution by analyzing fault effects of good scan chains, which are ignored by most previous works. Experimental results demonstrate the effectiveness of the proposed method.

Helix Scan: A Scan Design for Diagnosis

Scan design is a widely used design-for-testability technique to improve test quality and efficiency. For the scan-designed circuit, test and diagnosis of the scan chain and the circuit is an important process for silicon debug and yield learning. However, conventional scan designs and diagnosis methods abort the subsequent diagnosis process after diagnosing the scan chain if the scan chain is faulty. In this work, we propose a design-for-diagnosis scan strategy called helix scan and a diagnosis algorithm to address this issue. Unlike previous proposed methods, helix scan has the capability to carry on the diagnosis process without losing information when the scan chain is faulty. What is more, it simplifies scan chain diagnosis and achieves high diagnostic resolution as well as accuracy. Experimental results demonstrate the effectiveness of our design.

An algorithmic technique for diagnosis of faulty scan chains

This paper presents an algorithmic scan-chain-fault diagnosis procedure. The diagnosis for a single scan-chain fault is performed in three steps. The first step uses special chain test patterns to determine both the faulty chain and the fault type in the faulty chain. The second step uses a novel procedure to identify the suspect scan cell within a range of scan cells. The final step further improves the diagnostic resolution by ranking the suspect scan cells inside this range. The proposed technique handles both stuck-at and timing failures (transition faults and hold-time faults). The application of the procedure in a production test flow is discussed. Simulation and silicon results from several products show the effectiveness of the proposed method.