Complementary Metal Oxide Semiconductor Scaling Research Articles

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology.

After more than five decades, Moore's Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.

High-Performance P- and N-Type SiGe/Si Strained Super-Lattice FinFET and CMOS Inverter: Comparison of Si and SiGe FinFET.

This research presents the optimization and proposal of P- and N-type 3-stacked Si0.8Ge0.2/Si strained super-lattice FinFETs (SL FinFET) using Low-Pressure Chemical Vapor Deposition (LPCVD) epitaxy. Three device structures, Si FinFET, Si0.8Ge0.2 FinFET, and Si0.8Ge0.2/Si SL FinFET, were comprehensively compared with HfO2 = 4 nm/TiN = 80 nm. The strained effect was analyzed using Raman spectrum and X-ray diffraction reciprocal space mapping (RSM). The results show that Si0.8Ge0.2/Si SL FinFET exhibited the lowest average subthreshold slope (SSavg) of 88 mV/dec, the highest maximum transconductance (Gm, max) of 375.2 μS/μm, and the highest ON-OFF current ratio (ION/IOFF), approximately 106 at VOV = 0.5 V due to the strained effect. Furthermore, with the super-lattice FinFETs as complementary metal-oxide-semiconductor (CMOS) inverters, a maximum gain of 91 v/v was achieved by varying the supply voltage from 0.6 V to 1.2 V. The simulation of a Si0.8Ge0.2/Si super-lattice FinFET with the state of the art was also investigated. The proposed Si0.8Ge0.2/Si strained SL FinFET is fully compatible with the CMOS technology platform, showing promising flexibility for extending CMOS scaling.

Ring Oscillator for 60 Meter Bandwidth

The 60-meter band range is tremendously useful in telecommunication, military and governmental applications. The I. T. U. (International Telecommunication Union) required isolationism to former radio frequency services because the various frequency bands are extremely overloaded. The allocation of new frequency bands are a lengthy procedure as well as time taking. As a result, the researchers use bidirectional, amateur radio frequency communication for 60-meter band, usually the frequency slot of 5250–5450 KHz, although the entire band is not essentially obtainable for all countries. For transmission and reception of these frequencies, a local oscillator is used in the mixer unit to generate the local signal for mixing the input and reference signals. For this function different type of oscillators are used. In this paper, a three-stage ring oscillator is designed with 1 V supply. Ring oscillators (RO) is the base to explore like to identifying, specify with modelling resources in the disparity in behaviour of the circuit in terms of industrialized design and layout parameters. This type of oscillators are free from noise as inductor is not used to the circuit as in LC oscillator, Heartly oscillator, Colpitt and tuned oscillators. The present approach of circuit designing, the scaling of CMOS (Complementary Metal Oxide Semiconductor) transistor will moderate, the procedure variability. In the forthcoming article, a ring oscillator with fixed capacitor (1 pF) and with variable capacitors (1 to 100 pF) is analysed. The frequency analysis with different capacitor is performed. The total delay of 3-stage oscillator is 4.82 ns with 5.2 MHz oscillation frequency. The overall Power dissipation of the circuit is 1.852 μW at 1 V supply. The simulation analysis is performed on 45 nm CMOS technology with both transistor width are 278 and 420 nm.

Tightly Stacked 3D Diamond-Shaped Ge Nanowire Gate-All-Around FETs With Superior nFET and pFET Performance

We propose that the use of tightly stacked three-dimensional (3D) diamond-shaped Ge nanowire (NW) gate-all-around field-effect transistor (Ge-NW GAAFET) is a feasible approach to continuous scaling. The proposed devices with the Al₂O₃ dielectric exhibit high I_SAT of 1200 <inline-formula> <tex-math notation="LaTeX">$\boldsymbol {\mu } \text{A}/\boldsymbol {\mu } \text{m}$ </tex-math></inline-formula> (pFET) and 1100 <inline-formula> <tex-math notation="LaTeX">$\boldsymbol {\mu } \text{A}/\boldsymbol {\mu } \text{m}$ </tex-math></inline-formula> (nFET), high I_ON/I_OFF ratio of approximately <inline-formula> <tex-math notation="LaTeX">${1} \times {10}^{{5}}$ </tex-math></inline-formula>, and steep subthreshold swing (SS) close to 70mV/dec. Superior gate control of the Ge-NW GAAFET was confirmed by the 3D TCAD simulation for the sub-3nm node applications. The formation of the tightly stacked Ge NWs is fully compatible with the complementary metal oxide semiconductor (CMOS) technology platform using only alternating isotropic and anisotropic dry etching, thus showing promising potential for extending CMOS scaling in the vertical direction.

ALL-DIGITAL PHASE LOCKED LOOP (ADPLL) TOPOLOGIES FOR RFID SYSTEM APPLICATION: A REVIEW

An all-digital phase locked loop (ADPLL)-based local oscillator (LO) of RF transceiver application such as radio-frequency identification (RFID) system has gained popularity by accessing the benefits in complementary metal-oxide semiconductor (CMOS) process technology. This paper reviews some state-of-art of the ADPLL structures based on their applications and analyses its major implementation block, which is the digital-controlled oscillator (DCO). The DCO is evaluated based on its CMOS scaling and its performance in ADPLL, such as the power consumption, the chip area, the frequency range, the supply voltage, and the phase noise. Based on the review, the reduction in CMOS scaling decreases the transistor size in ADPLL design which leads to a smaller area and a low power dissipation. The combination of the time-to-digital (TDC) and the digital-to-time converter (DTC) that is used as the phase-frequency detector (PFD) in ADPLL is proposed to reduce the power and phase noise performance due to their high linearity design. The delay cell oscillator is found to consume more power at higher operating frequency, but it has an advantage of having less complexity and consuming less power and area in the circuit compared to the LC tank oscillator. For future work, it is recommended that an ADPLL-based LO of RFID transceiver with lowest voltage supply implementation is chosen and the use of the TDC-less as the PFD is selected due to its small area. While for the DCO, the delay cell will be designed due to its simpler implementation and occupy small area.

Emerging Fluorite‐ and Wurtzite‐Type Ferroelectrics: From (Hf,Zr)O2 to AlN and Related Materials

Emerging Fluorite‐ and Wurtzite‐Type Ferroelectrics: From (Hf,Zr)O₂ to AlN and Related Materials

Leakage reduction technique for nano-scaled devices

PurposeThe purpose of this paper is to propose a leakage reduction technique which will works for complementary metal oxide semiconductor (CMOS) and fin field effect transistor (FinFET). Power consumption will always remain one of the major concerns for the integrated circuit (IC) designers. Presently, leakage power dominates the total power consumption, which is a severe issue. It is undoubtedly clear that the scaling of CMOS revolutionizes the IC industry. Still, on the contrary, scaling of the size of the transistor has raised leakage power as one of the significant threats to the IC industry. Scaling of the devices leads to the scaling of other device parameters, which includes threshold voltage also. The scaling of threshold voltage leads to an exponential increase in the sub-threshold current. So, many leakage reduction techniques have been proposed by researchers for CMOS from time to time. Even the other nano-scaled devices such as FinFET, carbon nanotube field effect transistor and tunneling field effect transistor, have been introduced, and FinFET is the one which has evolved as the most favorable candidate for replacing CMOS technology.Design/methodology/approachBecause of its minimum leakage and without having limitation of the short channel effects, it gradually started replacing the CMOS. In this paper, the authors have proposed a technique for leakage reduction for circuits using nano-scaled devices such as CMOS and FinFET. They have compared the proposed PMOS FOOTER SLEEP with the existing leakage reduction techniques such as LECTOR technique, LECTOR FOOTER SLEEP technique. The proposed technique has been implemented using CMOS and FinFET devices. This study found that the proposed method reduces the average power, as well as leakage power reduction, for both CMOS and FinFET devices.FindingsThis study found that the proposed method reduces the average power as well as leakage power reduction for both CMOS and FinFET devices. The delay has been calculated for the proposed technique and the existing techniques, which verifies that the proposed technique is suitable for high-speed circuit applications. The authors have implemented higher order gates to verify the performance of the proposed circuit. The proposed method is suitable for deep-submicron CMOS technology and FinFET technology.Originality/valueAll the existing techniques were proposed for either CMOS device or FinFET device, but the authors have implemented all the techniques with both the devices and verified with the proposed technique for CMOS as well as FinFET devices.

Quantum physics applied to modern optical metal oxide semiconductor transistor

In recent years, traditional complementary metal–oxide–semiconductor (CMOS) scaling techniques have begun to reach the technological limits of available materials. A revolution in block-to-block communication is necessary to meet the ever-growing demand for microprocessor computational power. On-chip optical communication has been designated as a promising solution to circumvent the CMOS scaling bottlenecks: second-order phenomenon, which causes significant interconnect delays, and the nonscalability of the thermal voltage, which becomes significant in submicron CMOS technology. The metal oxide semiconductor quantum well transistor, a silicon-on-insulator metal–oxide–semiconductor field-effect transistor device, with a channel thickness reduced to the single nanometer scale is examined. The nanometric gate oxide, silicon, and buried oxide heterostructure in the channel forms a quantum potential well, creating discrete sub-bands within the silicon layer. Inter-sub-band-transitions within the quantum well may allow for radiative recombination in indirect band gap materials.

New Logic-In-Memory Paradigms: An Architectural and Technological Perspective.

Processing systems are in continuous evolution thanks to the constant technological advancement and architectural progress. Over the years, computing systems have become more and more powerful, providing support for applications, such as Machine Learning, that require high computational power. However, the growing complexity of modern computing units and applications has had a strong impact on power consumption. In addition, the memory plays a key role on the overall power consumption of the system, especially when considering data-intensive applications. These applications, in fact, require a lot of data movement between the memory and the computing unit. The consequence is twofold: Memory accesses are expensive in terms of energy and a lot of time is wasted in accessing the memory, rather than processing, because of the performance gap that exists between memories and processing units. This gap is known as the memory wall or the von Neumann bottleneck and is due to the different rate of progress between complementary metal–oxide semiconductor (CMOS) technology and memories. However, CMOS scaling is also reaching a limit where it would not be possible to make further progress. This work addresses all these problems from an architectural and technological point of view by: (1) Proposing a novel Configurable Logic-in-Memory Architecture that exploits the in-memory computing paradigm to reduce the memory wall problem while also providing high performance thanks to its flexibility and parallelism; (2) exploring a non-CMOS technology as possible candidate technology for the Logic-in-Memory paradigm.

Analysis of electron transport in the nano-scaled Si, SOI and III-V MOSFETs: Si/SiO2 interface charges and quantum mechanical effects

The ITRS predicts that the scaling of planar CMOS (Complementary Metal Oxide Semiconductor) technology will continue till the 22 nm technology node [1] and a possible extension beyond is appealing [2]. In this work, we investigate the effect of electron confinement [3] in nanoscaled transistor channels of 25 nm surface channel Si and 32 nm SOI (Silicon on Insulator) and 15 nm IF (Implant Free) III-V MOSFETs using a self-consistent solution of 1 D Poisson - Schrödinger equation [4,5]. For simulat ion and development with accuracy of nano-scaled of 25 nm gate length Si MOSFET (Metal Oxide Semiconductor Field Effect Transistor), 32 nm SOI Implant Free (IF) MOSFET, and 15nm Implant Free III-V MOSFET transistors, we investigated the bandstructure and quantum confinement effects occurring near the oxide-semiconductor interface inmetal-Oxide-Semiconductor (MOS) structure of Si MOSFET device. These investigation have been carried out using a selfconsistent solution of 1D Poisson-Schrödinger equation across the channel of conventional Si / SOI / III-V MOSFET Transistors. To solve self-consistently 1D Poisson-Schrödinger equations across the channel of a conventional Si, SOI, and an Implant Free III-V MOSFETs to determine the conduction and valence band profiles, electron density, electron sheet density, eigenstate and eigenfunctions in these structures. We present the simulat ion results of conduction band profile, electron density (classical and quantum mechanical), eigenstate and eigenfunctions for Si, SOI and III-V MOSFET structures at two different bias voltages of 0.5 V and 1.0 V. For comparison, we calculate the electron sheet density (quantum mechanically) as a function of the applied gate voltages.

Quantum dot cellular automata: A new paradigm for digital design

Quantum Dot Cellular Automata (QCA) is a newly developed paradigm for digital design, which holds the potential to be the possible alternative to the present CMOS (Complementary Metal Oxide Semi-Conductor) technology. After surviving for nearly five decades, the scaling of CMOS is finally reaching its limits. The asperities are not only seen from the physical and technological viewpoint but also from the material and economical perspectives. With no more scaling possible, there arises a need to look for promising alternatives to continue with the nano size/scale computations and to hold on to the Moore’s law. QCA offers a breakthrough required for the fulfilment of certain lacking aspects of CMOS technology in the nano regime. QCA is a technology that involves no current transfer but works on electronic interaction between the cells. The QCA cell basically consists of quantum dots or metal islands separated by certain distance and the entire transmission of information occurs via the interaction between the electrons localized in these potential wells. Since the technology is new and in a premature phase, a huge scope lies ahead of the researchers to investigate and make QCA designing a reality. In this paper the QCA technology is reviewed with sufficient focus on basic concepts, implementations and information flow. The various building blocks in QCA are discussed and their working on the basis of physical laws is explained. This paper forms the basis for further complex digital designing in QCA.

Correction of SNM (Static Noise Margin) of SRAM Using BTI (Bias Temperature Instability) Sensor

The continuous scaling of CMOS (Complementary Metal-Oxide-semiconductor) technology exponentially increases the power density per unit area (means temperature) and other effects such as lifetime reliability. Bias temperature instability (BTI) is the serious effect which originates due to scaling of MOS, the effect of BTI on the design of SRAM (Static Random-Access Memory); it decreases the static noise margin (SNM) of the SRAM. In this paper, a prototype BTI sensor is proposed, which is used for correction of SNM of SRAM. It is designed on 15 nm technology and simulated in Hspice in Cadence 6.15; the precision found after simulation is under 1.15 mV (±3% approx) for 1-V supply.

Unsupervised image processing scheme for transistor photon emission analysis in order to identify defect location

The study of the light emitted by transistors in a highly scaled complementary metal oxide semiconductor (CMOS) integrated circuit (IC) has become a key method with which to analyze faulty devices, track the failure root cause, and have candidate locations for where to start the physical analysis. The localization of defective areas in IC corresponds to a reliability check and gives information to the designer to improve the IC design. The scaling of CMOS leads to an increase in the number of active nodes inside the acquisition area. There are also more differences between the spot’s intensities. In order to improve the identification of all of the photon emission spots, we introduce an unsupervised processing scheme. It is based on iterative thresholding decomposition (ITD) and mathematical morphology operations. It unveils all of the emission spots and removes most of the noise from the database thanks to a succession of image processing. The ITD approach based on five thresholding methods is tested on 15 photon emission databases (10 real cases and 5 simulated cases). The photon emission areas’ localization is compared to an expert identification and the estimation quality is quantified using the object consistency error.

Experimental observation of voltage amplification using negative capacitance for sub-60 mV/decade CMOS devices

In this study, an experimental study of negative capacitance is performed in order to overcome the physical limit of subthreshold slope (SS), SS ≥ 60mV/decade at 300 K, which is originated from (i) using the thermionic emission process in complementary metal-oxide-semiconductor (CMOS) technology and (ii) non-scalability of the thermal voltage kBT/q (i.e., in order to realize SS lower than 60mV/decade at 300 K). To make the surface potential higher than the gate voltage, a step-up voltage amplifier is included in the CMOS gate stack using a ferroelectric capacitor implemented with ferroelectric material. The measured SS in long-channel CMOS transistors is 13 mV per decade at 300 K. A simple connection of the ferroelectric capacitor to a complementary metal oxide semiconductor (CMOS) gate electrode would provide a new evolutionary pathway for future CMOS scaling.

Exploiting sub-20-nm complementary metal-oxide semiconductor technology challenges to design affordable systems-on-chip

For the past four decades, cost and features have driven complementary metal-oxide semiconductor (CMOS) scaling. Severe lithography and material limitations seen below the 20-nm node, however, are challenging the fundamental premise of affordable CMOS scaling. Just continuing to co-optimize leaf cell circuit and layout designs with process technology does not enable us to exploit the challenges of sub-20-nm CMOS. For affordable scaling, it is imperative to work past sub-20-nm technology impediments while exploiting its features. To this end, we propose to broaden the scope of design technology co-optimization (DTCO) to be more holistic by including microarchitecture design and computer-aided design, along with circuits, layout, and process technology. Furthermore, we undertook such a holistic DTCO for all critical design elements such as embedded memory, standard cell logic, analog components, and physical synthesis in a 14-nm process. Measurements results from experimental designs in a representative 14-nm process from IBM demonstrate the efficacy of the proposed approach.

Reliability Study of Single Stage Multi-Input Majority Function for QCA

Due to the physical limitations faced by CMOS (Complementary Metal Oxide Semiconductor) scaling many technologies were suggested to replace CMOS on the nanoscale. Most of the suggested technologies are not deterministic and follow the Law of Large Number LLN. So, the reliability inspection is essential to these technologies. In this paper the PTM (Probabilistic Transfer Matrix) is used to inspect the reliability of multi-input majority function for QCA (Quantum dot-Cellular Automata). This study conclude that the single-gate with multi-input Majority has the same reliability of its 3-input form. To extend the results to digital circuits, the full adder is used as a test bench. The results show the superiority of the full adder version designed with 5input majority gate upon other designs from reliability point of view. General Terms Reliability in emerging technologies

A Novel Nanoinjection Lithography (NInL) Technology and Its Application for 16-nm Node Device Fabrication

For more than 45 years, photon- and electron-sensitive materials have been used to produce pattern-transfer masks in the lithographic manufacturing of integrated circuits. With the semiconductor technology feature size continuing to shrink and the requirements of low-variability and low-cost manufacturing, optical lithography is driven to its limits. In this paper, we report a novel nanoinjection lithography (NInL) technique that employs electron-beam-assisted deposition to form pattern-transfer hard mask in a direct-write deposit approach. By scanning the 4.6-nm-diameter electron beam while injecting a suitable organometallic precursor gas around the location of e-beam and just above the substrate, we form a high-density (pitch: 40 nm) high-uniformity (3-sigma linewidth roughness: 2 nm) hard mask for subsequent etching without using proximity-effect correction techniques. Furthermore, this technique can also directly deposit a metal pattern for interconnect or a dielectric pattern without the need for separate metal or dielectric deposition, photoresist etch-mask, and etching processes. The NInL approach simplifies the hard-mask creation or even metal or dielectric pattern creation process modules from five or tens of steps to only a single step. Therefore, it saves both photomask making and wafer processing costs. In addition, room-temperature NInL deposition of conductor/dielectric materials enables the fabrication of small versatile devices and circuits. For demonstration, we fabricated a functional 16-nm six-transistor static random access memory (SRAM) cell (area: occupying only 0.039 μm2), 43% the size of the smallest previously reported SRAM cell, using the FinFET structure and a dynamic Vdd regulator approach. The NInL technique offers a new way of exploring low-volume high-value 16-nm complementary metal-oxide-semiconductor (CMOS) devices and circuit designs with minimal additional investment and obtains early access to extreme CMOS scaling.

A New Differential-Amplifier-Based Offset-Cancellation Sense Amplifier for Speed-Improvement of High-Density Static Random Access Memories in Scaled-Down Complementary Metal–Oxide–Semiconductor Technology

A new differential-amplifier-based offset-cancellation sense amplifier (DOCSA) is proposed in order to improve operation speed of high-density, six-transistor-cell static random access memories (SRAMs) in scaled-down complementary metal–oxide–semiconductor (CMOS) technology. 40-nm node CMOS test chips were fabricated and measured to demonstrate the successful operation and performance of DOCSA. Simulated offset voltage of DOCSA was 60% compared to that of a conventional latch-type sense amplifier with the same input capacitance, and the bit-line delay in an SRAM is expected to be 60% by using DOCSA. The standard deviation of measured offset voltage in DOCSA agreed well with that of the simulated one. Combination of CMOS scaling and deviation-relief circuit technology becomes important in advanced LSI technology.

Patterning and Templating for Nanoelectronics

The semiconductor industry will soon be launching 32 nm complementary metal oxide semiconductor (CMOS) technology node using 193 nm lithography patterning technology to fabricate microprocessors with more than 2 billion transistors. To ensure the survival of Moore's law, alternative patterning techniques that offer advantages beyond conventional top-down patterning are aggressively being explored. It is evident that most alternative patterning techniques may not offer compelling advantages to succeed conventional top-down lithography for silicon integrated circuits, but alternative approaches may well indeed offer functional advantages in realising next-generation information processing nanoarchitectures such as those based on cellular, bioinsipired, magnetic dot logic, and crossbar schemes. This paper highlights and evaluates some patterning methods from the Center on Functional Engineered Nano Architectonics in Los Angeles and discusses key benchmarking criteria with respect to CMOS scaling.

Nanoarchitectonics for Heterogeneous Integrated Nanosystems

Based on projections of the International Roadmap for Semiconductors (ITRS), the continued scaling of complementary metal-oxide semiconductor (CMOS) devices will face severe technical challenges. Among the most critical are power dissipation and device-level variabilities that will make circuit design very difficult. Potential device-level solutions that take advantage of new functional materials, self-assembly processes, low dissipation nanoscale devices, and architectures that aim in sustaining Moore's law beyond the ITRS are discussed in this paper. Two potential paths forward are clear at this point. One path is to continue increasing chip-scale functional throughput by looking at new functional materials at atomic and molecular levels for assembly into new low-power devices with different logic state variables that can better tolerate variabilities. Another distinct approach is to increase chip-scale functionality by exploiting the heterogeneous integration of materials, such as compound semiconductors on silicon as enabled by the unique features in nanoscale epitaxy and self-assembly on a common substrate. This paper will discuss some possible methods forward in maintaining scaled CMOS and going beyond the roadmap.