Scalable POWERparallel System Research Articles

A Loop Transformation Algorithm for Communication Overlapping

Overlapping communication with computation is a well-known approach to improving performance. Previous research has focused on optimizations performed by the programmer. This paper presents a compiler algorithm that automatically determines the appropriate loop indices of a given nested loop and applies loop interchange and tiling in order to overlap communication with computation. The algorithm avoids generating redundant communication by providing a framework for combining information on data dependence, communication, and reuse. It also describes a method of generating messages to exchange data between processors for tiled loops on distributed memory machines. The algorithm has been implemented in our High Performance Fortran (HPF) compiler, and experimental results have shown its effectiveness on distributed memory machines, such as the RISC System/6000 Scalable POWERparallel System. This paper also discusses the architectural problems of efficient optimization.

Design of a video-server complex for interactive television

This paper describes the architecture and implementation of a scalable video server for interactive television services, which has been used in several video-on-demand projects in Japan. This server supports a large number of users with the delivery of high-quality video and provides many types of interactive multimedia applications. The server, using the IBM RISC System/6000® and RISC System/6000 Scalable POWERparallel Systems®, permits full interactive operation with clients. It also can deliver a large number of streams when it is expanded from a single-processor system to a multi-processor system, without any change of the server architecture. In this paper, we describe the end-to-end architecture, the design considerations regarding scalability of the delivery scheme for MPEG-2 transport streams, and the management mechanism for interactive applications. This paper also addresses the implementation of quality of service for digital services through a hybrid fiber-coax network infrastructure, and protocols for interactive television services.

Parallel solution of sparse linear least squares problems on distributed-memory multiprocessors

This paper studies the parallel solution of large-scale sparse linear least squares problems on distributed-memory multiprocessors. The key components required for solving a sparse linear least squares problem are sparse QR factorization and sparse triangular solution. A block-oriented parallel algorithm for sparse QR factorization has already been described in the literature. In this paper, new block-oriented parallel algorithms for sparse triangular solution are proposed. The arithmetic and communication complexities of the new algorithms applied to regular grid problems are analyzed. The proposed parallel sparse triangular solution algorithms together with the block-oriented parallel sparse QR factorization algorithm result in a highly efficient approach to the parallel solution of sparse linear least squares problems. Performance results obtained on an IBM Scalable POWERparallel system SP2 are presented. The largest least squares problem solved has over two million rows and more than a quarter million columns. The execution speed for the numerical factorization of this problem achieves over 3.7 gigaflops per second on an IBM SP2 machine with 128 processors.

A parallel implementation of a 3-D pseudospectral based code on the IBM 9076 scalable POWERparallel system

The paper reports on two parallel message passing implementations of a 3-D pseudospectral based code on top of the PVMe [1] and the MPL Parallel Environment [2], both parallel interfaces tuned for the IBM's scalable parallel system. Specifically, the discussion underlines details of high performing real-to-complex and complex-to-real parallel 3-D FFTs, the two computational kernels in the 3-D pseudospectral integration method, on the base of parallel performances measured on an SP1 16 nodes and on two SP2 16 thin and 16 wide nodes. At the end, some considerations about computational capabilities of the IBM's parallel distributed memory architecture in performing high intensive numerical simulations of 3-D homogeneous turbulent flows are also addressed.

CCL: a portable and tunable collective communication library for scalable parallel computers

A collective communication library for parallel computers includes frequently used operations such as broadcast, reduce, scatter, gather, concatenate, synchronize, and shift. Such a library provides users with a convenient programming interface, efficient communication operations, and the advantage of portability. A library of this nature, the Collective Communication Library (CCL), intended for the line of scalable parallel computer products by IBM, has been designed. CCL is part of the parallel application programming interface of the recently announced IBM 9076 Scalable POWERparallel System 1 (SP1). In this paper, we examine several issues related to the functionality, correctness, and performance of a portable collective communication library while focusing on three novel aspects in the design and implementation of CCL: 1) the introduction of process groups, 2) the definition of semantics that ensures correctness, and 3) the design of new and tunable algorithms based on a realistic point-to-point communication model. >

Status and issues of HPF compilers

AbstractHigh Performance Fortran (HPF) is an emerging, de facto standard language for machine‐independent, data‐parallel programs that run on various parallel machines. The ease with which parallel programs can be created by means of simple data placement annotations to Fortran 90 programs is particularly attractive to end‐users. The success of the HPF approach, however, depends on the innovation in compiler technology. In order to achieve a reasonable speedup on the target parallel machine, the HPF compiler must be able to parallelize loops, optimize communications, localize arrays, and generate efficient, scalable single‐program multiple‐data (SPMD) code. We have implemented HPF on the basis of the IBM XL Fortran 90 compiler. This task will present an overview of our compilation strategy and preliminary results obtained on an IBM Scalable POWERparallel System.

A scalable implementation of the NAS Parallel Benchmark BT on distributed memory systems

In this paper, we describe an efficient and scalable implementation of the NAS Parallel Benchmark BT suitable for distributed memory systems such as the IBM Scalable POWERparallel Systems®. After describing the parallelization and data partitioning methods used, we outline some of the optimization steps used to realize good performance on individual processors and to reduce the communication overheads on the IBM SP1™ and SP2™ systems. We present performance results on up to 128 nodes of the SP1, and on the SP2 with wide nodes. We describe the performance on the standard Class A and Class B problem sets. To show the scalability of our parallelization methods, we present the performance of two additional data sets.

Preface

The growth of technical and commercial applications for high-performance computing, combined with the decline in the price of computers overall and the need to deliver new capabilities quickly, has led to the emergence of parallel computers and parallel computing. The newest of the desired applications include digital libraries, transaction processing, decision support, advanced multimedia, high-bandwidth networks, and data mining. Current high-performance applications from business and science also need a path to effective use of parallel computing. IBM has addressed this broad new territory with solutions that are general purpose and scalable and that operate readily within existing technical and commercial computing environments. These solutions are built on the firm foundation of RISC System/6000* workstation microprocessors with the AIX* operating system or on the well-established System/390* enterprise servers. The former solution—the IBM Scalable POWERparallel Systems*—is the focus of this special issue.