Scalable Field Programmable Gate Array Research Articles

Method of creation of FPGA based implementation of artificial intelligence as a service

The subject of study in this article is the technologies of Field Programmable Gate Array (FPGA), methods, and tools for prototyping of hardware accelerators of Artificial Intelligence (AI) and providing it as a service. The goal is to reduce the efforts of creation and modification of FPGA implementation of Artificial Intelligent projects and provide such solutions as a service. Task: to analyze the possibilities of heterogeneous computing for the implementation of AI projects; analyze advanced FPGA technologies and accelerator cards that allow the organization of a service; analyze the languages, frameworks, and integrated environments for the creation of Artificial Intelligence projects for FPGA implementation; propose a technique for modifiable FPGA project prototyping to ensure a long period of compatibility with integrated environments and target devices; propose a technique for the prototyping of FPGA services with high performance to improve the efficiency of FPGA based AI projects; propose a sequence of optimization of neural networks for FPGA implementation; and provide an example of the practical implementation of the research results. According to the tasks, the following results were obtained. Analysis of the biggest companies and vendors of FPGA technology is performed. Existing heterogeneous technologies and potential non-electronic mediums for AI computations are discussed. FPGA accelerator cards with a large amount of High Bandwidth Memory (HBM) on the same chip package for implementation of AI projects are analyzed and compared. Languages, frameworks, and technologies as well as the capabilities of libraries and integrated environments for prototyping of FPGA projects for the AI applications are analyzed in detail. The sequence of prototyping of FPGA projects that are stable to changes in the environment is proposed. The sequence of prototyping of highly efficient pipelined projects for data processing is proposed. The steps of optimization of neural networks for FPGA implementation of AI applications are provided. An example of practical use of the results of research, including the use of sequences is provided. Conclusions. One of the main contributions of this research is the proposed method of creation of FPGA based implementation of AI projects in the form of services. Proposed sequence of neural network optimization for FPGA allows the reduction of the complexity of the initial program model by more than five times for hardware implementation depending on the required accuracy. The described solutions allow the construction of completely scalable and modifiable FPGA implementations of AI projects to provide it as a service.

Hardware-friendly tone-mapping operator design and implementation for real-time embedded vision applications

Tone-mapping is required to convert High Dynamic Range (HDR) images to Low Dynamic Range (LDR) images for viewing on standard displays. Most recent works in the domain include the efficient implementation of tone-mapping algorithms on Graphics Processing Units (GPUs) for throughput improvements. However, their downside is significantly high power consumption, making such solutions unsuitable for displays on embedded and general consumer electronic devices. In contrast, Field Programmable Gate Arrays (FPGAs) have demonstrated significant speedup on data-intensive image and video applications with a much lower power consumption than GPUs. This paper proposes a modular, scalable and resource-efficient FPGA implementation of a global Tone-Mapping Operator (TMO) based on histogram of the scene luminance and characteristics of the Human Visual System (HVS). Compared to GPU based implementation of a state-of-the-art TMO, our FPGA implementation achieved a higher throughput in the range of 2.5× to 4.5× with power savings of more than two orders of magnitude. Moreover, tonal quality of the proposed solution is better than the baseline TMO in approximately 80% of a dataset of 288 HDR images. The proposed solution also outperformed the state-of-the-art FPGA implementations of other TMOs in throughput, resource usage and scalability.

FPGA-Based Architecture for Sensing Power Consumption on Parabolic and Trapezoidal Motion Profiles

The objective of this work is to design and implement a scalable Field-Programmable Gate Array (FPGA)-based motion control system for DC servo motors using a parabolic velocity profile for industrial applications. The implementation in this device allows the obtaining of a fast, flexible and low-cost system. The system is divided into control, communication and closed-loop coupling. The work also addresses a comparative analysis of the most used profiles, the trapezoidal and parabolic. The comparison is made considering the energy consumption of both profiles. As a consequence of the comparison made, the velocity profile can be selected to reduce production costs by saving energy and reducing wear on machinery. The discrete models of the velocity profiles are obtained through numerical methods that permit the control blocks to be implemented in an FPGA. To reduce maintenance costs and energy consumption in servo mechanisms, the derivation of the acceleration or jerk of the motor is shown. A Graphic User Interface (GUI) is presented, which allows monitoring the position, velocity and angular acceleration of the motor shaft. In addition, the developed interface supports modification of parameters of the final position and maximum velocity in the motor. The delivered current is compared, evaluating its decrease using a parabolic velocity profile. Finally, the experimental results are illustrated.

Weighted p -Bits for FPGA Implementation of Probabilistic Circuits.

Probabilistic spin logic is a recently proposed computing paradigm based on unstable stochastic units called probabilistic bits ( p -bits) that can be correlated to form probabilistic circuits (p-circuits). These p-circuits can be used to solve the problems of optimization, inference, and implement precise Boolean functions in an "inverted" mode, where a given Boolean circuit can operate in reverse to find the input combinations that are consistent with a given output. In this brief, we present a scalable field-programmable gate array implementation of such invertible p-circuits. We implement a "weighted" p -bit that combines stochastic units with localized memory structures. We also present a generalized tile of weighted p -bits to which a large class of problems beyond invertible Boolean logic can be mapped and how invertibility can be applied to interesting problems such as the NP-complete subset sum problem by solving a small instance of this problem in hardware.

Latency Insertion Method Based Real-Time Simulation of Power Electronic Systems

In this paper, we demonstrate how latency insertion method (LIM) can be used for real-time simulation of high switching frequency power electronics systems and how this approach can be implemented for scalable Field Programmable Gate Array (FPGA) execution. We first present a summary of the LIM and how this method can be developed into a solver for high-performance FPGA execution. We then present how common power electronics topologies—buck and boost—can be modeled using the LIM approach, followed by how the LIM model of a three-phase dc/ac converter is created. Afterward, we demonstrate the accuracy of the developed FPGA solver through a set of power electronic system examples, with each example compared with near ideal results of same example provided by a traditional electromagnetic transient type solver. We complete the paper analyzing the scalability of the proposed approach on FPGA devices, both in terms of achievable time step as well as of resource usage.

A Reconfigurable and Scalable FPGA Architecture for Bilateral Filtering

Bilateral filter is an edge-preserving smoother that has applications in image processing, computer vision, and computational photography. In the past, fieldprogrammable gate array (FPGA) implementations of the filter have been proposed that can achieve high throughput using parallelization and pipelining. An inherent limitation with direct implementations is that their complexity scales as O(ω <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) with the filter width ω. In this paper, we propose an FPGA implementation of a fast bilateral filter that requires just O(1) operations for any arbitrary ω. The attractive feature of the FPGA implementation is that it is both scalable and reconfigurable. To the best of our knowledge, this is the first scalable FPGA implementation of the bilateral filter. As an application, we use the FPGA implementation for image denoising.

A Generic Reconfigurable Mixed Time and Frequency Domain QAM Transmitter with Forward Error Correction

In the past three decades, Field Programmable Gate Arrays (FPGAs) have emerged to be the backbone of digital signal processing, especially in high-speed communication systems. However, today, these devices are clocked below 1GHz and improvement in performance stays a big challenge on all abstraction layers, right from system architecture down to physical technology. Far and wide, myriad number of researches are done on methodologies and techniques which can deliver higher throughput with lower operating frequencies. Towards this projected objective, in this paper an efficient modulation technique like Quadrature Amplitude Modulation (QAM) along with mixed time and frequency domain approach and Forward Error Correction (FEC) technique have been utilized to employ a generic scalable FPGA based QAM transmitter with filter parallelization being executed in mixed domain. The system developed in this paper achieves an effective throughput of 12.8Gb/s for 256-QAM with 16 parallel inputs having an operating frequency of 201.25MHz, while a 18.7Gb/s effective throughput is realized with 32 parallel inputs at 146MHz. Thereby, it paves down a promising methodology for applications where having higher clock frequencies is a hard limit.

Simple scalable nucleotic FPGA based short read aligner for exhaustive search of substitution errors

Abstract With the advent of the new and continuously improving technologies, in a couple of years DNA sequencing can be as commonplace as a simple blood test. The growth of sequencing efficiency has a larger exponent than the Moore’s law of standard processors, hence alignment and further processing of sequenced data is the bottleneck. The usage of FPGA (Field Programmable Gate Arrays) technology may provide an efficient alternative. We propose a simple algorithm for DNA sequence alignment, which can be realized efficiently by nucleotic principal agents of Non.Neumann nature. The prototype FPGA implementation runs on a small Terasic DE1-SoC demo board with a Cyclone V chip. We present test results and furthermore analyse the theoretical scalability of this system, showing that the execution time is independent of the length of reference genome sequences. A special advantage of this parallel algorithm is that it performs exhaustive search producing all match variants up to a predetermined number of point (mutation) errors.

Scalable FPGA Refurbishment Using Netlist-Driven Evolutionary Algorithms

In this work, Field-Programmable Gate Array (FPGA) reconfigurability is exploited to realize autonomous fault recovery in mission-critical applications at runtime. The proposed Netlist-Driven Evolutionary Refurbishment technique utilizes design-time information from the circuit netlist to constrain the search space of the algorithm by up to 98.1 percent in terms of the chromosome length representing reconfigurable logic elements. This facilitates refurbishment of relatively large-sized FPGA circuits as compared to previous works. Hence, the scalability issue associated with Evolvable Hardware-Based refurbishment is addressed and improved. Experiments are conducted with multiple circuits from the MCNC benchmark suite to validate the approach and assess its benefits and limitations. Successful refurbishment of the apex4 circuit having a total of 1,252 LUTs with 10 percent spares is achieved in as few as 633 generations on average when subjected to simulated randomly injected single stuck-at faults. Moreover, the use of design-time information about the circuit undergoing refurbishment is validated as means to increase the tractability of dynamic evolvable hardware techniques.

Novel cascade FPGA accelerator for support vector machines classification.

Support vector machines (SVMs) are a powerful machine learning tool, providing state-of-the-art accuracy to many classification problems. However, SVM classification is a computationally complex task, suffering from linear dependencies on the number of the support vectors and the problem's dimensionality. This paper presents a fully scalable field programmable gate array (FPGA) architecture for the acceleration of SVM classification, which exploits the device heterogeneity and the dynamic range diversities among the dataset attributes. An adaptive and fully-customized processing unit is proposed, which utilizes the available heterogeneous resources of a modern FPGA device in efficient way with respect to the problem's characteristics. The implementation results demonstrate the efficiency of the heterogeneous architecture, presenting a speed-up factor of 2-3 orders of magnitude, compared to the CPU implementation. The proposed architecture outperforms other proposed FPGA and graphic processor unit approaches by more than seven times. Furthermore, based on the special properties of the heterogeneous architecture, this paper introduces the first FPGA-oriented cascade SVM classifier scheme, which exploits the FPGA reconfigurability and intensifies the custom-arithmetic properties of the heterogeneous architecture. The results show that the proposed cascade scheme is able to increase the heterogeneous classifier throughput even further, without introducing any penalty on the resource utilization.

An analytical model for multilevel performance prediction of Multi-FPGA systems

Power limitations in semiconductors have made explicitly parallel device architectures such as Field-Programmable Gate Arrays (FPGAs) increasingly attractive for use in scalable systems. However, mitigating the significant cost of FPGA development requires efficient design-space exploration to plan and evaluate a range of potential algorithm and platform choices prior to implementation. The authors propose the RC Amenability Test for Scalable Systems (RATSS), an analytical model which enables straightforward, fast, and reasonably accurate performance prediction prior to implementation by extending current modeling concepts to multi-FPGA designs. RATSS provides a comprehensive strategic model to evaluate applications based on the computation and communication requirements of the algorithm and capabilities of the FPGA platform. The RATSS model targets data-parallel applications on current scalable FPGA systems. Three case studies with RATSS demonstrate nearly 90% prediction accuracy as compared to corresponding implementations.

StarPlace: A new analytic method for FPGA placement

To date, the best algorithms for performing placement on Field-Programmable Gate Arrays (FPGAs) are based on Simulated Annealing (SA). Unfortunately, these algorithms are not scalable due to the long convergence time of the latter. With an aim towards developing a scalable FPGA placer we present an analytic placement method based on a near-linear net model, called star+. The star+ model is a variant of the well-known star model and is continuously differentiable – a requirement of analytic methods that rely on the existence of first- and second-order derivatives. Most importantly, with the star+ model incremental changes in cost resulting from block movement can be computed in O(1) time, regardless of the size of the net. This makes it possible to construct time-efficient solution methods based on conjugate gradient and successive over-relaxation for solving the resulting non-linear equation system. When compared to VPR, the current state-of-the-art placer based on SA, our analytic method is able to obtain an 8–9% reduction in critical-path delay while achieving a speedup of nearly 5x when VPR is run in its fast mode.

Hardware accelerated FPGA placement

A key advantage of field-programmable gate arrays (FPGAs) over full-custom and semi-custom devices is that they provide relatively quick implementation from concept to physical realization. However, as modern FPGAs reach close to one million logic blocks, more efficient and scalable FPGA placement algorithms are needed. This paper investigates the feasibility of using hardware acceleration, in the form of FPGAs, to improve the performance of placement algorithms. An iterative algorithm is presented which exploits the fine-grain parallelism in routing individual nets. Overall, our results show that speedups of 3–4 times can be obtained, without sacrificing solution quality.

Post-Placement Interconnect Entropy

We introduce the concept of post-placement interconnect entropy: the minimal number of bits required to describe a well-placed netlist, which has connection lengths distributed according to Rent's rule. The entropy is a function of the number N of cells in the netlist and the Rent exponent p. We derive an expression for the entropy per cell and show that it converges as N approaches infinity. The entropy provides an achievable lower bound on the number of configuration bits in a programmable logic device (PLD) [or field-programmable gate array (FPGA)] and a useful measure of its routing flexibility. Specific numerical values are computed for practical situations. For example, any scalable FPGA composed of 4-input lookup table cells would require 31 configuration bits per cell. We compare this to the actual number of configuration bits in a standard FPGA architecture. We generalize the bound to dimensions higher than two, and show that for any p there is an optimal dimension that minimizes the bound.

An FPGA-Based Approach to High-Speed Simulation of Conductance-Based Neuron Models

The constant requirement for greater performance in neural model simulation has created the need for high-speed simulation platforms. We present a generalized, scalable field programmable gate array (FPGA)-based architecture for fast computation of neural models and focus on the steps involved in implementing a single-compartment and a two-compartment neuron model. Based on timing tests, it is shown that FPGAs can outperform traditional desktop computers in simulating these fairly simple models and would most likely provide even larger performance gains over computers in simulating more complex models. The potential of this method for improving neural modeling and dynamic clamping is discussed. In particular, it is believed that this approach could greatly speed up simulations of both highly complex single neuron models and networks of neurons. Additionally, our design is particularly well suited to automated parameter searches for tuning model behavior and to real-time simulation.