Scalable Communication Architecture Research Articles

Design and Implementation of a Fully-Actuated Integrated Aerial Platform Based on Geometric Model Predictive Control

Unlike individual unmanned aerial vehicles (UAVs), integrated aerial platforms (IAPs) containing multiple UAVs do not suffer from underactuation and can move omnidirectionally in six dimensions, providing a basis for constructing aerial manipulation platforms. Compared to single UAVs, multi-UAV IAPs are also advantageous in terms of payload and fault-tolerance capacity, making them promising candidates as platforms with integrated-response, observation, and strike capabilities. Herein, an IAP structure design containing three sub-UAVs connected in a star-like configuration is presented. This form of integration enables the IAP, as a whole, to simultaneously adjust its position and attitude in six dimensions. The dynamics of the overall system of the IAP are modeled. On this basis, an overall system controller is designed. To simplify control, based on stability of cascaded system, the rotational motion of the sub-UAVs is treated as a inner-loop subsystem, whereas the overall motion of the IAP is seen as a outer-loop subsystem. Because the configuration space of the sub-UAVs is non-Euclidean, a controller is designed for the outer-loop subsystem based on model predictive control on the manifold. Subsequently, the stability of the closed-loop system is demonstrated. Fieldbus technology is employed to design a real-time, scalable communication architecture for multiple sub-UAVs, followed by the development of a principle prototype of the multi-UAV IAP that consists of hardware and software systems. The effectiveness of the IAP design and control method is validated through simulation and real-world prototype-based tests. In the simulation and real-world tests, the proposed methodology can make the IAP system converge to the desired configuration at the presence of large initial configuration error. The same test scenario cannot be finished by a baseline PID controller. The advantage of the proposed control scheme in dealing with state and input constraints is shown via such tests.

A Roadmap Toward a Unified Space Communication Architecture

In recent years, the number of space exploration missions has multiplied. Such an increase raises the question of effective communication between the multitude of human-made objects spread across our solar system. An efficient and scalable communication architecture presents multiple challenges, including the distance between planetary entities, their motion and potential obstruction, the limited available payload on satellites, and the high mission cost. This paper brings together recent relevant specifications, standards, mission demonstrations, and the most recent proposals to develop a unified architecture for deep-space internetworked communication. After characterizing the transmission medium and its unique challenges, we explore the available communication technologies and frameworks to establish a reliable communication architecture across the solar system. We then draw an evolutive roadmap for establishing a scalable communication architecture. This roadmap builds upon the mission-centric communication architectures in the upcoming years towards a fully interconnected network or InterPlanetary Internet (IPN). We finally discuss the tools available to develop such an architecture in the short, medium, and long terms. The resulting architecture cross-supports space agencies on the solar system-scale while significantly decreasing space communication costs. Through this analysis, we derive the critical research questions remaining for creating the IPN regarding the considerable challenges of space communication.

A smart Internet of Things–based mechanism for wireless communications in NoC

With the development of silicon integration technology, the network-on-chip (NoC) proposes a scalable communication architecture that can improve system performance. Future multi-core chips are expected to be heterogeneous and hierarchical in nature. Inter-frequency interference will occur between various 2.4-GHz wireless network communication cores integrated on the same chip, resulting in lower network throughput and higher communication latency. This article solves the problem of wireless co-channel mutual interference from the two aspects of time domain and frequency domain and designs a heterogeneous platform based on NoC architecture to achieve more stable parallel communication of multiple wireless co-frequency networks without mutual interference. When the system detects the interference, this article uses the chirped fractional Fourier transform to filter out the interference signal before the signal arrives and then spreads the frequency. According to the results, the method improves the anti-interference ability of the network and the utilization of spectrum resources. Compared with the traditional carrier sense multiple access method, the spectrum-aware channel cooperation method proposed in this article reduces the data average transmission delay by 0.02 s and the data packet reception rate is increased by about 30%, which provides a certain reference value for future wireless multi-core communication.

A neuro-inspired artificial peripheral nervous system for scalable electronic skins.

The human sense of touch is essential for dexterous tool usage, spatial awareness, and social communication. Equipping intelligent human-like androids and prosthetics with electronic skins-a large array of sensors spatially distributed and capable of rapid somatosensory perception-will enable them to work collaboratively and naturally with humans to manipulate objects in unstructured living environments. Previously reported tactile-sensitive electronic skins largely transmit the tactile information from sensors serially, resulting in readout latency bottlenecks and complex wiring as the number of sensors increases. Here, we introduce the Asynchronously Coded Electronic Skin (ACES)-a neuromimetic architecture that enables simultaneous transmission of thermotactile information while maintaining exceptionally low readout latencies, even with array sizes beyond 10,000 sensors. We demonstrate prototype arrays of up to 240 artificial mechanoreceptors that transmitted events asynchronously at a constant latency of 1 ms while maintaining an ultra-high temporal precision of <60 ns, thus resolving fine spatiotemporal features necessary for rapid tactile perception. Our platform requires only a single electrical conductor for signal propagation, realizing sensor arrays that are dynamically reconfigurable and robust to damage. We anticipate that the ACES platform can be integrated with a wide range of skin-like sensors for artificial intelligence (AI)-enhanced autonomous robots, neuroprosthetics, and neuromorphic computing hardware for dexterous object manipulation and somatosensory perception.

A efficacy of different buffer size on latency of network on chip (NoC)

Moore's prediction has been used to set targets for research and development in semiconductor industry for years now. A burgeoning number of processing cores on a chip demand competent and scalable communication architecture such as network-on-chip (NoC). NoC technology applies networking theory and methods to on-chip communication and brings noteworthy improvements over conventional bus and crossbar interconnections. Calculated performances such as latency, throughput, and bandwidth are characterized at design time to assured the performance of NoC. However, if communication pattern or parameters set like buffer size need to be altered, there might result in large area and power consumption or increased latency. Routers with large input buffers improve the efficiency of NoC communication while routers with small buffers reduce power consumption but result in high latency. This paper intention is to validate that size of buffer exert influence to NoC performance in several different network topologies. It is concluded that the way in which routers are interrelated or arranged affect NoC’s performance (latency) where different buffer sizes were adapted. That is why buffering requirements for different routers may vary based on their location in the network and the tasks assigned to them.

Impact Studies and Cooperative Voltage Control for High PV Penetration

Abstract The drastically increasing penetration of photovoltaic (PV) has posed tremendous challenges in operation, control, and protection in distribution networks. The over-voltage issue is one of major concerns for extremely high PV penetration (e.g. 100%). It is critical to identify the most sensitive locations to high PV penetration and apply effective methods to mitigate the over-voltage issue. This paper introduced a novel greedy search algorithm to locate worst-case scenarios of over-voltage in both distributed and centralized PV configurations, as well as a cooperative voltage control method to mitigate over-voltage. The search algorithm has the computational advantage over existing stochastic approach and provides more insights in impact studies. The cooperative control method relies upon reactive power compensation to converge system voltage to a predefined value within standard limits. Moreover, a clustering strategy is applied to divide the network into several clusters, within which all nodes share information with neighboring nodes following a scalable communication architecture. The control algorithms and communication hierarchies presented in this paper have been implemented into OpenDSS to form the Multi Agent (MA) OpenDSS package, which has been made available to the reader. The effectiveness of developed methods are demonstrated through simulation studies on the IEEE 123-node test feeder under four different load levels.

Scalable communication architectures for massively parallel hardware multi-processors

Modern complex embedded applications in multiple application fields impose stringent and continuously increasing functional and parametric demands. To adequately serve these applications, massively parallel multi-processor systems on a single chip (MPSoCs) are required. This paper is devoted to the design of scalable communication architectures of massively parallel hardware multi-processors for highly-demanding applications. We demonstrated that in the massively parallel hardware multi-processors the communication network influence on both the throughput and circuit area dominates the processors influence, while the traditionally used flat communication architectures do not scale well with the increase of parallelism. Therefore, we propose to design highly optimized application-specific partitioned hierarchical organizations of the communication architectures through exploiting the regularity and hierarchy of the actual information flows of a given application. We developed related communication architecture synthesis strategies and incorporated them into our quality-driven model-based multi-processor design methodology and related automated architecture exploration framework. Using this framework we performed a large series of architecture synthesis experiments. Some of the results of the experiments are presented in this paper. They demonstrate many features of the synthesized communication architectures and show that our method and related framework are able to efficiently synthesize well scalable communication architectures even for the high-end massively parallel multi-processors that have to satisfy extremely stringent computation demands.

Communication and Memory Architecture Design of Application‐Specific High‐End Multiprocessors

This paper is devoted to the design of communication and memory architectures of massively parallel hardware multiprocessors necessary for the implementation of highly demanding applications. We demonstrated that for the massively parallel hardware multiprocessors the traditionally used flat communication architectures and multi‐port memories do not scale well, and the memory and communication network influence on both the throughput and circuit area dominates the processors influence. To resolve the problems and ensure scalability, we proposed to design highly optimized application‐specific hierarchical and/or partitioned communication and memory architectures through exploring and exploiting the regularity and hierarchy of the actual data flows of a given application. Furthermore, we proposed some data distribution and related data mapping schemes in the shared (global) partitioned memories with the aim to eliminate the memory access conflicts, as well as, to ensure that our communication design strategies will be applicable. We incorporated these architecture synthesis strategies into our quality‐driven model‐based multi‐processor design method and related automated architecture exploration framework. Using this framework, we performed a large series of experiments that demonstrate many various important features of the synthesized memory and communication architectures. They also demonstrate that our method and related framework are able to efficiently synthesize well scalable memory and communication architectures even for the high‐end multiprocessors. The gains as high as 12-times in performance and 25-times in area can be obtained when using the hierarchical communication networks instead of the flat networks. However, for the high parallelism levels only the partitioned approach ensures the scalability in performance.

A quantitative evaluation of a Network on Chip design flow for multi-core consumer multimedia applications

A growing number of applications are integrated on the same System on Chip in the form of hardware and software Intellectual Property (IP). Many applications have firm or soft real-time requirements and require bounds on latency and throughput. To accommodate the growing number of application requirements, the on-chip interconnect must offer scalability on the physical, architectural and functional level. Networks on Chip (NoC) are proposed as a scalable communication architecture that is also able to deliver guaranteed performance. Traditionally, NoCs focus on delivering physical and architectural scalability. The functional scalability, i.e. the ability to satisfy an increasing number of increasingly demanding requirements with a constant cost/performance ratio, is often overlooked. The onus is on the interconnect design flow that translates user requirements to an interconnect instance. While mature tooling exists for many of the IPs, interconnect design flows are an active research area, with few concrete examples, and few large-scale case studies. As the main contribution of this work, we demonstrate a complete operational interconnect design flow for multiple real-time applications, and quantitatively evaluate the functional scalability on two large-scale industrial case studies. We illustrate the steps of the flow, going from requirement specification all the way to simulation of synthesised netlists in a 90 nm and 65 nm low-power standard-cell technology. We show that the interconnect and design flow offer scalability, on the physical, architectural as well as the functional level.

Switcherland

Computer systems have become powerful enough to process continuous data streams such as video or animated graphics. While processing power and communication bandwidth of today's systems typically are sufficient, quality of service (QoS) guarantees as required for handling such data types cannot be provided by these systems in adequate ways.We present Switcherland, a scalable communication architecture based on crossbar switches that provides QoS guarantees for workstation clusters in the form of reserved bandwidth and bounded transmission delays. Similar to the ATM technology Switcherland provides QoS guarantees with the help of service classes, that is, data transfers are characterized as variable bit rate traffic or constant bit rate traffic. However, unlike LAN technologies, Switcherland is optimized for cluster computing in that (i) it serves as a backplane interconnection fabric as well as a LAN, (ii) it extends support for service classes by also covering the end nodes of the network, (iii) it provides low latency in the order of one microsecond per switch, and (iv) it uses a communication model based on a global memory to simplify programming.