Scalable ATM Switch Research Articles

An architecture of scalable ATM switching system and its performance

In this paper, we present the basic idea and some concepts for the architecture of the ATM switching system being developed in ETRI of KOREA, and also describe its performance. RSE (Reference Service Entity) concept is introduced to define the characteristics of user's traffic. This concept is useful to represent the demand of CPE (Customer Premise Equipment) user sets and one of point?to?multipoint connections. We also propose RUCA (Reference Units for Connection Attempts) concept with which we can illustrate the call/connection level performance of the ATM switching system. This concept can be applied for measuring the call processing capability in both point?to?multipoint connections and multipoint?to?multipoint connections when call set?up between users is performed by a sequence of point?to?point connections basis. From the basic concepts and the recommendations of ITU?T, the design objective of the system performance is specified. We represent the methodologies for dimensioning the system to achieve the design objectives, and estimate the system performances. Then we show that our developing system has suitable performance to accommodate the future B?ISDN.

Architecture, defect tolerance, and buffer design for a new ATM switch

This paper presents a modular architecture for a scalable ATM-switch. The cell routing function, as well as the associated queueing, are distributed over many small clusters of nodes, called basic modules. These basic modules are hierarchically interconnected to form larger switches. In a basic module, every node is interconnected with adjacent nodes in the same module with three of its four links. The fourth link is used to connect either to an external port or to other basic modules at higher levels of the hierarchy. From a hardware implementation perspective, the simplicity of the architecture stems from the fact that each node in the switch consists of two small crossbar switches of low complexity, a buffer, and a controller. The hierarchial nature of the topology allows for modular growth of the switch. Further, the interconnection topology of the switch makes it suitable for three-dimensional (3-D) (stacked VLSI) implementation.

An ATM routing and concentration chip for a scalable multicast ATM switch

We have proposed a new architecture for building a scalable multicast ATM switch from a few tens to a few thousands of input/output ports. The switch, called the Abacus switch, employs input and output buffering schemes. Cell replication, cell routing, and output contention resolution are all performed in a distributed way so that the switch can be scaled up to a large size. The Abacus switch adopts a novel algorithm to resolve the contention of both multicast and unicast cells destined for the same output port (or output module). The switch can also handle multiple priority traffic by routing cells according to their priority levels. This paper describes a key ASIC chip for building the Abacus switch. The chip, called the ATM routing and concentration (ARC) chip, contains a two-dimensional array (3/spl times/32) of switch elements that are arranged in a cross-bar structure. It provides the flexibility of configuring the chip into different group sizes to accommodate different ATM switch sizes. The ARC chip has been designed and fabricated using 0.8-/spl mu/m CMOS technology and tested to operate correctly at 240 MHz, Although the ARC chip was designed to handle the line rate at OC-3 (155 Mb/s), the Abacus switch can accommodate a much higher line rate at OC-12 (622 Mb/s) or OC-48 (2.5 Gb/s) by using a bit-sliced technique or distributing cells in a cyclic order to different inputs of the ARC chip. When the latter scheme is used, the cell sequence is retained at the output of the Abacus switch.

Scalable shared-buffering ATM switch with a versatile searchable queue

The shared-buffering architecture is promising to make a large-scale ATM switch with small buffer size. However, there are two important problems, namely, memory-access speed and complex-control implementation. Advanced 0.5 /spl mu/m CMOS technology now makes it possible to integrate a huge amount of memory, and enables us to apply more sophisticated architecture than ever before. We propose the funnel-structured expandable architecture with shared multibuffering and the advanced searchable-address queueing scheme for these two problems. The funnel structure gives a flexible capability to build various sizes of ATM switches which are proportional to the number of LSI chips. The searchable-address queue, in which all the addresses of the stored cells for different output ports are queued in a single-FIFO hardware and the earliest address is found by the search function provided inside the queue, can reduce the total memory capacity drastically, and enables the address queue to be contained inside the LSI chip. This technique also has a great advantage for implementing the multicast and multilevel priority-control functions. A 622 Mbit/s 32/spl times/8 ATM switch LSI chip set, which consists of a BX-LSI and a CX-LSI, is developed using 0.5 /spl mu/m pure CMOS technology. By using four chip sets, a 622 Mbit/s 32/spl times/32 switch can be installed on one board.

Design and implementation of Abacus switch: a scalable multicast ATM switch

Describes a new architecture for a multicast ATM switch scalable from a few tens to a few thousands of input ports. The switch, called the Abacus switch, has a nonblocking switch fabric followed by small switch modules at the output ports. It has buffers at input and output ports. Cell replication, cell routing, output contention resolution, and cell addressing are all performed in a distributed way so that it can be scaled up to thousands of input and output ports. A novel algorithm has been proposed to resolve output port contention while achieving input buffers sharing, fairness among the input ports, and call splitting for multicasting. The channel-grouping mechanism is also adopted in the switch to reduce the hardware complexity and improve the switch's throughput, while the cell sequence integrity is preserved. The switch can also handle multiple priority traffic by routing cells according to their priority levels. The performance study of the Abacus switch in throughput, average cell delay, and cell loss rate is presented. A key ASIC chip for building the Abacus switch, called the ARC (ATM routing and concentration) chip, contains a two-dimensional array (32/spl times/32) of switch elements that are arranged in a crossbar structure. It provides the flexibility of configuring the chip into different group sizes to accommodate different ATM switch sizes. The ARC chip has been designed and fabricated using 0.8 /spl mu/m CMOS technology and tested to operate correctly at 240 MHz.

An Architecture of Scalable ATM Switching and Its Call Processing Capacity Estimation

In this paper, we define the general requirements of ATM switching systems such as scalability, distributed fashion, and modularity. Also we propose a practical implementation of a scalable ATM switching system whose capacity can be easily expanded. Firstly, the architecture of the system is discussed with an emphasis on system scalability, modularity of subsystems and the simple control network of the design requirements. Secondly, we suggest the three types of distributed call/connection control schemes that are suitable for our switching system. We also estimate their call processing capacity on the average and make a comparison of them under the various system architectures. Since our scalable switching system can be constructed to perform the call processing functions on the various levels of the system capacity, it has much adaptability at the various evolution phases or regions of the network environment.

Modelling and performance assessment of large ATM switching networks on loosely-coupled parallel processors

A parallel simulation tool has been developed with the aim of evaluating the performance of a class of ATM switching systems. In this paper, the class of ATM switching networks of interest and the corresponding modelling are addressed. An appropriate decomposition scheme is revealed with respect to the model being built. The performance of the parallel tool is examined, based on a scalable ATM switching network, by means of a loosely-coupled parallel computer system. A combination of general purpose and problem specific algorithms results in a high computational efficiency, portability and scalability.