Savings In Power Consumption Research Articles

Forecasting-Based Dynamic Virtual Channel Management for Power Reduction in Network-on-Chips

In this paper, a forecasting-based dynamic virtual channel allocation technique for reducing the power consumption of network on chips is introduced. Based on the network traffic as well as past link and total virtual channel utilizations, the technique dynamically forecasts the number of virtual channels that should be active. It is based on an exponential smoothing forecasting method that filters out short-term traffic fluctuations. In this technique, for low (high) traffic loads, a small (large) number of VCs are allocated to the corresponding input channel. To assess the efficacy of the proposed method, the network on chip has been simulated using uniform, transpose, hotspot, NED, and realistic GSM voice codec traffic profiles. Simulation results show that up to a 35% reduction in the buffer power consumption and up to 20% savings in the overall router power consumption may be achieved. The area and power dissipation overheads of the technique are negligible.

시멘트 포장공정에서 환기시스템에 따른 발생분진의 제어

시멘트 포장공정에서 발생하는 비산분진을 효율적으로 제거하기 위해 3가지 환기방식(국소배기시스템, 정전식스크러버시스템, 국소급기시스템)을 도입하고 풍량을 변화시키며 총 9가지의 조건에서 실험을 수행하였다. 분진의 농도는 시멘트분진 입자분포 특성을 고려하여 PM2.5, PM10, TSP로 구분하여 측정하였다. 3가지 환기방식에 대한 집진효율을 분석한 결과, 기존의 국소배기시스템과 정전식스크러버시스템이 같이 사용되는 경우 가장 효율적인 것으로 나타났다. 또한 정정식스크러버시스템의 풍량 증가에 따른 입자의 질량농도감소율이 큰 차이가 없는 것을 확인할 수 있었고 이로부터 정정식스크러버시스템을 <TEX>$2,700m^3/h$</TEX> 풍량으로 운전하는 것이 에너지절약 관점에서 효율적인 것이라고 판단되었다. 각 환기방식별 환기성능을 국소배기시스템의 풍량으로 환산한 결과, 대체시스템(정전식스크러버시스템, 국소급기시스템)분진제거성능이 우수한 젓으로 나타났고 정전식스크러버시스템이 국소급기시스템보다 상당히 효율적인 것으로 나타났다. 따라서 기존의 국소배기시스템파 정전식스크러버시스템을 동시에 가동한다면 국소배기시스템의 풍량만을 증가시키는 경우에 비해 반송동력을 줄일 수 있어 분진제거와 에너지절감측면에서 훨씬 효율적이라는 것을 알 수 있었다. We performed the experimental study on the control of suspended dust in a cement packaging process for various ventilation systems. To effectively remove the dust generated in the cement packaging process, three different kinds of ventilation system, such as local exhaust ventilation, electrostatic scrubber, and local air supply system, were adopted. Dust concentrations in the packaging process were measured with the variation of the airflow rate of the ventilation systems and then their ventilation performance were evaluated. From the results, we knew that the ventilation performance was the best when the local exhaust ventilation and the electrostatic scrubber were simultaneously operated in the packaging process. In the electrostatic scrubber system, the effect of the airflow rate on the indoor dust removal efficiency was negligible so hat he system ust be operated at <TEX>$2,700m^3/h$</TEX> for saving power consumption.

Optimal Ladder Filters

Optimizing the dynamic range of active filters through filter network optimization can lead to significant savings in chip area and power consumption. By restricting the filters to be ladder filters, it is possible to limit the complexity of the optimized networks.

CLOCK DISTRIBUTION NETWORKS WITH GRADUAL SIGNAL TRANSITION TIME RELAXATION FOR REDUCED POWER CONSUMPTION

Clock distribution network consumes a significant portion of the total chip power since the clock signal has the highest activity factor and drives the largest capacitive load in a synchronous integrated circuit. A new methodology is proposed in this paper for buffer insertion and sizing in an H-tree clock distribution network. The objective of the algorithm is to minimize the total power consumption while satisfying the maximum acceptable clock transition time constraints at the leaves of the clock distribution network for maintaining high performance. The new methodology employs nonuniform buffer insertion and progressive relaxation of the transition time requirements from the leaves to the root of the clock distribution network. The proposed algorithm provides up to 30% savings in the total power consumption without sacrificing clock skew as compared to a standard algorithm with uniform buffer insertion aimed at maintaining uniform transition time constraints at all the nodes of a clock tree in a 180 nm CMOS technology.

Caches for Multimedia Workloads: Power and Energy Tradeoffs

One of the significant workloads in current generation desktop processors and mobile devices is multimedia processing. Large on-chip caches are common in modern processors, but large caches will result in increased power consumption and increased access delays. Regular data access patterns in streaming multimedia applications and video processing applications can provide high hit-rates, but due to issues associated with access time, power and energy, caches cannot be made very large. Characterizing and optimizing the memory system is conducive for designing power and performance efficient multimedia application processors. Performance tradeoffs for multimedia applications have been studied in the past, however, power and energy tradeoffs for caches for multimedia processing have not been adequately studied in the past. In this paper, we characterize multimedia applications for I-cache and D-cache power and energy using a multilevel cache hierarchy. Both dynamic and static power increase with increasing cache sizes, however, the increase in dynamic power is small. The increase in static power is significant, and becomes increasingly relevant for smaller feature sizes. There is significant static power dissipation, ~ 45%, in L1 & L2 caches at 70 nm technology sizes, emphasizing the fact that future multimedia systems must be designed by taking leakage power reduction techniques into account. The energy consumption of on-chip L2 caches is seen to be very sensitive to cache size variations. Sizes larger than 16 k for I-caches and 32 k for D-caches will not be efficient choices to maintain power and performance balance. Since multimedia applications spend significant amounts of time in integer operations, to improve the performance, we propose implementing low power full adders and hybrid multipliers in the data path, which results in 9% to 21% savings in the overall power consumption.

Energy-Efficient Digital Predistortion With Lookup Table Training Using Analog Cartesian Feedback

We demonstrate energy-efficient low-complexity adaptive linearization for wideband handset power amplifiers (PAs). Due to power overhead and complexity, traditional wideband linearization techniques such as adaptive digital predistortion (DPD) thus far have not been used for wideband handset transmitters. Our energy-efficient lookup table training strategy resulted in a training energy of 1.83 nJ/entry for a 5-MHz bandwidth WiMAX orthogonal frequency division multiple access (OFDMA) transmission, which represents more than 40times improvement over state-of-the-art DPD implementations. Our experimental prototype transmitter achieves a maximum of 9.9-dB improvement of adjacent channel leakage power at 5.15-MHz offset with 22.0-dBm channel power in the 5-MHz bandwidth WiMAX-OFDMA transmission. This linearity improvement offers 26.5% savings in PA power consumption by reducing power backoff.

Race-Free Mixed Serial-Parallel Comparison for Low Power Content Addressable Memory

This letter presents a race-free mixed serial-parallel comparison (RFMSPC) scheme which uses both serial and parallel CAMs in a match line. A self-reset search line scheme for the serial CAM is proposed to avoid the timing race problem and additional timing penalties. Various 32 entry CAMs are designed using 90 nm 1.2 V CMOS process to verify the proposed RFMSPC scheme. It shows that the RFMSPC saves power consumption by 40%, 53% and 63% at the cost of a 4%, 6% and 16% increase in search time according to 1, 2, and 4 serial CAM bits in a match line.

Design and Implementation of Modular FPGA-Based PID Controllers

In this paper, modular design of embedded feedback controllers using field-programmable gate array (FPGA) technology is studied. To this end, a novel distributed-arithmetic (DA)-based proportional-integral-derivative (PID) controller algorithm is proposed and integrated into a digital feedback control system. The DA-based PID controller demonstrates 80% savings in hardware utilization and 40% savings in power consumption compared to the multiplier-based scheme. It also offers good closed-loop performance while using less resources, resulting in cost reduction, high speed, and low power consumption, which is desirable in embedded control applications. The complete digital control system is built using commercial FPGAs to demonstrate the efficiency. The design uses a modular approach, so that some modules can be reused in other applications. These reusable modules can be ported into Matlab/Simulink as Simulink blocks for hardware/software cosimulation or integrated into a larger design in the Matlab/Simulink environment to allow for rapid prototyping applications.

Development of large area gamma-ray camera with GSO(Ce) scintillator arrays and PSPMTs

We have developed a position-sensitive scintillation camera with a large area as an absorber of an advanced Compton gamma-ray camera. At first we tested GSO(Ce) crystals. We compared light output from the GSO(Ce) crystals under various conditions: the method of surface polishing, the concentration of Ce, and co-doping Zr. As a result, we chose the GSO(Ce) crystals doped only 0.5 mol% Ce, surface of which was polished by chemical etching for the scintillator of our camera. We also made a 16 × 16 cm 2 scintillation camera which consisted of nine position-sensitive PMTs (PSPMTs Hamamatsu flat-panel H8500 ), the each of which had 8 × 8 anodes with a pitch of 6 mm and coupled to 8 × 8 arrays of pixelated 6 × 6 × 13 mm 3 GSO(Ce) scintillators. For the readout system of 576 anodes of the PMTs, we used chained resistors to reduce the number of readout channels down to 48 for saving power consumption. The camera has the position resolution of less than 6 mm and a typical energy resolution of 10.5% (FWHM) at 662 keV at each pixel in a large area of 16 × 16 cm 2 . Furthermore, we constructed a 16 × 16 array of 3 × 3 × 13 mm 3 pixelated GSO(Ce) scintillators, and glued it to a PMT H8500. This camera had the position resolution of less than 3 mm in area of 5 × 5 cm 2 , except for some of edge pixels; the energy resolution was typically 13% (FWHM) at 662 keV.

A power-aware motion estimation architecture using content-based subsampling

This paper presents a novel power-aware motion estimation architecture for battery-powered multimedia devices. As the battery status changes, the proposed architecture adaptively performs graceful tradeoffs between power consumption and compression quality. The tradeoffs are considered to be graceful in that the proposed architecture is scalable with changing conditions and the compression quality is slightly degraded as the available energy is depleted. The key to such tradeoffs lies in a content-based subsample algorithm, first proposed in this paper. As the available energy decreases, the algorithm raises the subsample rate for maximizing the battery lifetime. Differently from the existing subsample algorithms, the content-based algorithm first extracts edge pixels from a macro-block and then subsamples the remaining low-frequency part. By doing so, we can alleviate the aliasing problem and, thus, limit the quality degradation as the subsample rate increases. Given a power consumption mode, the proposed architecture first performs edge extraction to generate a turn-off mask and then uses the turn-off mask to reduce the switch activities of processing elements (PEs) in a semi-systolic array. The reduction of switch activities results in significant power consumption savings. To achieve a high degree of scalability and qualified power-awareness, we use an adaptive control mechanism to set the threshold value for edge determination and make the reduction of switch activities rather stationary. As shown by experimental results, the architecture can dynamically operate in different power consumption modes with little quality degradation according to the remaining capacity of the battery pack while the power overhead of edge extraction is kept under 0.8%

Efficient rate control for JPEG-2000

In this paper, we present two new methods for efficient rate control and entropy coding in lossy image compression using JPEG-2000. These two methods enable significant improvements in computation complexity and power consumption over the traditional JPEG-2000 algorithms. First, we propose a greedy heap-based rate-control algorithm (GHRaC), which achieves efficient postcompression rate control by implementing a greedy marginal analysis method using the heap sort algorithm. Second, we propose an integrated rate-control and entropy-coding (IREC) algorithm that reduces the computation complexity of entropy coding by selectively entropy coding only the image data that is likely to be included in the final bitstream, as opposed to entropy coding all image data. Together, these two methods enable significant savings in computation time and power consumption. For example, the GHRaC method demonstrates 16 /spl times/ speedup for rate control when encoding the Lena color image using a target compression ratio of 128:1, one quality layer, and code blocks of 32 /spl times/ 32 pixels. The IREC method expands upon GHRaC to perform entropy coding in conjunction with rate control. Using an enhanced version of IREC, these two methods jointly achieve a speedup in execution time of 14 /spl times/ over traditional rate control and entropy coding, which first entropy codes all image coefficients and then separately performs postcompression rate control using the generalized Lagrange multiplier method to select which data are included in the final bitstream. Both theoretical analysis and empirical results are presented in validating the advantages of the proposed methods.

Low-voltage CMOS circuits for analog iterative decoders

Iterative decoders, including Turbo decoders, provide near-optimal error protection for various communication channels and storage media. CMOS analog implementations of these decoders offer dramatic savings in complexity and power consumption, compared to digital architectures. Conventional CMOS analog decoders must have supply voltage greater than 1 V. A new low-voltage architecture is proposed which reduces the required supply voltage by at least 0.4 V. It is shown that the low-voltage architecture can be used to implement the general sum-product algorithm. The low-voltage analog architecture is then useful for implementing Turbo and low-density parity check decoders. The low-voltage architecture introduces new requirements for signal normalization, which are discussed. Measured results for two fabricated low-voltage analog decoders are also presented.

ON THE DESIGN OF EFFICIENT MODULAR ADDERS

Modular adders are met in various applications of computer systems. In this paper, we investigate a new architecture for their design that utilizes a carry save adder stage and two binary adders that operate in parallel. Realizations in static CMOS reveal that the introduced architecture leads to modular adder implementations that offer significant savings in delay and power consumption over implementations based on previously proposed architectures. In parallel, the proposed architecture offers significantly smaller implementation area for small operand widths.

A novel generic fast Fourier transform pruning technique and complexity analysis

The fast Fourier transform (FFT) is an essential tool in digital signal processing and communications. In the applications of the FFT where the required outputs are very sparse, for example, in digital filtering, one may only require the spectrum corresponding to certain bins of the FFT or in narrow frequency windows. In these cases, most of the FFT outputs are not required. Some pruning algorithms have been proposed to deal with such cases. However, most of the pruning algorithms require that the outputs be in continuous windows. This paper develops a traced FFT Pruning method (TFFTP), which is a novel technique and does not require this condition. Under some circumstances, considerable savings in computational complexity and power consumption can be realized using the TFFTP compared to the FFT. This paper derives the average number of butterflies that need to be executed when only k/sub in/ input or/and k/sub out/ output bins of an N point FFT, where k/sub in//spl les/N, or/and k/sub out//spl les/N are required. This method is then extended to arbitrary radix FFT pruning and simultaneous input and output pruning case.

Execution cache-based microarchitecture for power-efficient superscalar processors

This paper investigates a possible solution to the problem of power consumption in superscalar, out-of-order processors by proposing a new microarchitecture, specifically designed to reduce increasing power requirements of high-end processors. More precisely, we show that by modifying the well-established superscalar processor architecture, significant savings can be achieved in terms of power consumption. Our approach aims at limiting the growing amount of power used in a typical processor for dynamic optimizations (including out-of-order scheduling and register renaming). Our proposed approach achieves significant power savings by reusing as much as possible from the work done by the front-end of a typical superscalar, out-of-order pipeline, via the use of a special cache nested deeply into the processor structure. By reusing instructions that are already decoded, reordered, and have their registers already renamed, the front end of the pipeline can be turned off for large periods of time with significant savings in the overall power consumption. Experimental results show up to 35% (30% on average) savings in average energy per committed instruction, and 35% (20% on average) savings in energy-delay product, with about 9% average performance loss, over a large spectrum of SPEC95 and SPEC2000 benchmarks.

Once-through and brine recirculation MSF designs — a comparative study

This study investigated the feasibility of the once-through (OT) MSF design for constructing large-capacity desalting plants rather than the conventional brine recycle (BR) MSF configuration. This was to explore the possibility of improving MSF process economics through the application of a simpler process design. It is known that the OT design is characterized by its simplicity and elimination of the brine recirculation pump as well as the rejection section. These features are expected to reduce capital and maintenance costs. The current study is based on comparing the two MSF plant configurations, OT and BR, from the standpoint of minimum heat transfer area, which is a major element in capital investment. Alternative tube layouts, long-tube (LT) and cross-tube (CT) arrangements, were considered. Design calculations were based on a plant capacity of 20 MGD, a gained output ratio of 10, a top brine temperature of 120°C, a feed temperature and concentration of 35°C and 48,000 ppm, respectively. The total number of stages was varied stepwise between 20 and 40. A rigorous mathematical model was developed to solve the optimization problem taking into consideration the nonlinearity of the thermo-physical properties of seawater and steam. The Solver tool of Microsoft Excel was used to determine the optimal solutions. Substantial savings in the heat transfer area can be realized through the application of the LT-OT design when the number of stages goes up to 40. However, comparison of the different MSF designs with the optimal number of stages and minimum heat transfer area tells us that the use of the OT designs is not likely to save more than 1% in heat transfer area relative to the conventional CT-BR configuration. Findings related to the specific chemical consumption are not in favor of OT plants where the consumption ratio varies between 1.7 and 1.9 relative to the CT-BR plants. Of course, excessive chemical consumption penalizes the operating cost of the OT plants. However, the increase in operating costs has to be weighed against the savings in capital cost and lower power consumption due to the elimination of the recycle pump and the heat rejection section. This will determine the use of the OT configuration for building MSF plants in the future. In this event, a detailed cost analysis will be needed.

블루투스 피코넷에서의 효율적인 전력 및 자원 스케줄링

근거리 무선 개인 네트워크 시스템 즉, 블루투스의 피코넷을 위한 전력 및 차등 대역폭 할당을 고려한다. 대역폭 요구는 어플리케이션/서비스에 또는 시간에 따라서 변할 수도 있으므로, 제한된 자원을 서비스 요구를 만족하면서 다양한 서비스 클래스로 어떻게 할당할 것인가를 결정 하는 것이 중요하다. 본 논문에서는 다양한 서비스 형태의 대역폭 요구를 만족하면서 전력 절약 모드 (즉, 스니프 모드)에 의해 전력 소비를 절약하는 간단하고 효율적인 대역폭 할당 메커니즘을 제안한다. 기존의 (가중치) 라운드 로빈 폴링 방법과 제안된 메커니즘을 비교하고, 전송율, 지연시간, 전력 소비 측면에서의 성능 향상을 보인다. We consider differentiated bandwidth allocation for a piconet in short-range wireless personal network systems : Bluetooth. Since bandwidth requirements nay vary among applications/services, and/or it may change over time, it is important to decide how to allocate limited resources to various service classes to meet their service requirements. We propose a simple and efficient bandwidth allocation mechanism which meets bandwidth requirements of various service types while saving power consumption by a Power saying mode, i.e., sniff node. We compare our proposed mechanism with a conventional (weighted) round-robin polling scheme and show that it achieves significant improvement of hroughput, delay, and power consumption.

Advanced Technologies for Read Channel on Blu-ray Disc

We propose advanced technologies to enhance the system performances of the Blu-ray disc (BD) system. The technologies are based on the read channel that we reported previously. Our previous read-channel was designed for a modulation code with Tmin (minimum length between transition) of 3 and whose fs (system clock frequency) was higher than 1.5×fc (channel rate). To achieve technical subjects such as robustness against asymmetry and noise on the BD, our target changed to a read-channel designed for a modulation code with Tmin of 2 (17pp modulation code). Furthermore, to achieve practical subjects for a production, the system clock frequency of the new read-channel became half-rate ( fs is higher than 0.75×fc) for saving power consumption, and the performance of the digital phase locked loop (DPLL) was reinforced for random access.

Sleep switch dual threshold Voltage domino logic with reduced standby leakage current

A circuit technique is presented for reducing the subthreshold leakage energy consumption of domino logic circuits. Sleep switch transistors are proposed to place an idle dual threshold voltage domino logic circuit into a low leakage state. The circuit technique enhances the effectiveness of a dual threshold voltage CMOS technology to reduce the subthreshold leakage current by strongly turning off all of the high threshold voltage transistors. The sleep switch circuit technique significantly reduces the subthreshold leakage energy as compared to both standard low-threshold voltage and dual threshold voltage domino logic circuits. A domino adder enters and leaves a low leakage sleep mode within a single clock cycle. The energy overhead of the circuit technique is low, justifying the activation of the proposed sleep scheme by providing a net savings in total power consumption during short idle periods.

환형 무전극 형광램프의 전자계 시뮬레이션, 전기적 및 광학적 특성

In recent, there have been several developments in lamp technology that promise savings in electrical power consumption and improved quality of the lighting space. Above all, the advantage of ring-shaped electrodeless fluorescent lamp is the removal of internal electrodes and heating filaments that are a light-limiting factor of conventional fluorescent lamps. The ring-shaped electrodeless lamp is intended as a high efficiency replacement for the incandescent reflector lamp in many applications. Therefore, the life time of ring-shaped electrodeless fluorescent lamps is substantially higher than that of conventional fluorescent lamps and last up to 60,000 hours. In this paper, maxwell 3D finite element analysis program(Ansoft) was used to obtain electromagnetic properties associated with the coil and nearby structures. The electromagnetic emitting properties were presented by 3D simulation software operated at 250 KHz and some specific conditions. The optical characteristics were measured luminance and a temperature and an optical spectrum distribution for 10 min in a one minute interval at the same time. With a goal of finding alternative materials, we show measurement results of electrical characteristics of a ring-shaped electrodeless fluorescent lamp as a function of frequency and the number of coil turns using a highly permeable(<TEX>$\mu$</TEX><TEX>$_{r}$</TEX>(equation omitted) 2,000) Mn-Zn ferrite. These results are compared with those of conventional ring-shaped electrodeless fluorescent lamp. It is found that the resistance, inductance and impedance are increased while the quality factor decreases as frequency increases.s.