SAT-based Automatic Test Pattern Generation Research Articles

On the Generation of Waveform-Accurate Hazard and Charge-Sharing Aware Tests for Transistor Stuck-Off Faults in CMOS Logic Circuits

Opens are known to be one of the predominant defects in nanoscale technologies. With an increasing number of complex cells in today’s very large-scale integration designs intracell opens are becoming a larger and larger problem. Typically, these defects are modeled by transistor stuck-off faults (TSOFs) and assumed to be detected by transition delay fault (TDF) timing tests. However, tests for TDF fail to detect a high percentage of TSOFs and even tools that target them directly are not sufficient to screen all open defects. Furthermore, generated tests might be invalidated in case hazards and charge-sharing are not properly considered. In this paper, we present a waveform-accurate SAT-based automatic test pattern generation (ATPG) framework to tackle these problems. The proposed method not only allows for the generation of tests that are robust against hazards and charge-sharing, it can also be used to generate tests for faults only detectable by hazard-based activation—and hence even increase the fault coverage beyond state-of-the-art cell-aware tests. Our experimental results for the largest ITC’99, IWLS 2005 as well as larger industrial circuits mapped to the state-of-the-art NanGate 45-nm as well as NanGate 15-nm cell library using complex cells show the high efficiency and scalability of the proposed method. For example, the results show that without properly considering hazards and charge-sharing up to 17.9% of the generated tests could be invalidated. In addition, hazard-activated ATPG allows to detect an additional 10.1% of conventionally undetectable faults that could result in a very significant defective parts per million improvement.

Evaluating the Effectiveness of D-chains in SAT-based ATPG and Diagnostic TPG

The ever increasing size and complexity of today’s Very-Large-Scale-Integration (VLSI) designs requires a thorough investigation of new approaches for the generation of test patterns for both test and diagnosis of faults. SAT-based automatic test pattern generation (ATPG) is one of the most popular methods, where, in contrast to classical structural ATPG methods, first a mathematical representation of the problem in form of a Boolean formula is generated, which is then evaluated by a specialized solver. If the considered fault is testable, the solver will return a satisfying assignment, from which a test pattern can be extracted; otherwise no such assignment can exist. In order to speed up test pattern generation, the concept of D-chains was introduced by several researchers. Thereby supplementary clauses are added to the Boolean formula, reducing the search space and guiding the solver toward the solution. In the past, different variants of D-chains have been developed, such as the backward D-chain or the indirect D-chain. In this work we perform a thorough analysis and evaluation of the D-chain variants for test pattern generation and also analyze the impact of different D-chain encodings on diagnostic test pattern generation. Our experimental results show that depending on the incorporated D-chain the runtime can be reduced tremendously.

A Two-Variable Model for SAT-Based ATPG

Automatic test pattern generation (ATPG) is one of the first applications that motivated the development of modern Boolean satisfiability (SAT). It is now widely accepted that ATPG is easy for current state-of-the-art SAT solvers. Nevertheless, as with any NP-hard problem, for large complex industrial circuits, some faults may be difficult to detect or prove undetectable. Recent work on SAT-based ATPG has been motivated by industrial designs with ever increasing size, for which more efficient ATPG models are essential. Moreover, ATPG models and algorithms find applications in a number of other settings, which further motivate the development of more efficient SAT-based ATPG solutions. Interestingly, despite the interest in more efficient ATPG approaches, the core SAT-based ATPG model has remained essentially unchanged since it was first proposed in the 1980s. This paper describes an alternative model for SAT-based ATPG. The proposed model is fundamentally different from previous SAT-based ATPG models in that the number of used variables is significantly reduced. This paper proposes extensions and optimizations to the basic model, and integrates known techniques for further improving performance. This paper extends the new model, proposes optimizations to it, and integrates known techniques for further improving performance. To achieve an unbiased evaluation, this paper also reimplements previous models and comprehensively compares them with the proposed models. Experimental results, obtained on a wide range of publicly available benchmarks for ATPG, demonstrate that the basic model and extended models allow significant performance improvements over other well-established models.

TG-Pro: A SAT-based ATPG System

Automatic Test Pattern Generation (ATPG) is arguably one of the practical applications that motivated the development of modern Boolean Satisfiability (SAT) solvers in the mid 90s. Despite the interest of using SAT in ATPG, the original model remained mostly unchanged for nearly two decades, even in the presence of renewed interest in applying modern SAT technology to large-scale hardware designs. This paper describes the SAT-based ATPG system TG-Pro. In contrast to all SAT-based ATPG work over the last two decades, TG-Pro is based on a new fundamentally different SAT-based ATPG model. Experimental results, obtained on well-known and publicly available benchmarks, demonstrate that TG-Pro achieves major performance improvements over other well-established SAT-based ATPG models.

Efficient Data Structures and Methodologies for SAT-Based ATPG Providing High Fault Coverage in Industrial Application

ATPG based on Boolean satisfiability (SAT) turned out to be a robust alternative to classical structural automatic test pattern generation (ATPG) algorithms performing very well especially for hard-to-detect faults but suffer from the overhead for easy-to-detect faults. In this letter, we propose new efficient data structures and methodologies for SAT-based ATPG. The novel incremental SAT solving technique dynamic clause activation which makes use of structural information using dedicated data structures forms the core of a new flexible SAT-based ATPG approach. Experimental results on large industrial circuits show a significant performance gain and a removal of the limitations. At the same time, the robustness of SAT-based ATPG can even be strengthened resulting in very high fault efficiency and increased fault coverage for transition faults.

Conflict-Driven Learning in Test Pattern Generation

SAT-based automatic test pattern generation (ATPG) is built on a SAT-solver, which can be scalable is that it is able to take into account the information of high-level structure of formulas. Paper analyzes specific structure of circuit instances where correlations among signals have been established. This analysis is a heuristic learning method by earlier detecting assignment conflicts. Reconvergent fanout is a fundamental cause of the difficulty in testing generation, because they introduce dependencies in the values that can be assigned to nodes. Paper exploits reconvergent fanout analysis of circuit to gather information about local signal correlation through BDD learning, and then used the learned information in the conjunctive normal form (CNF) clauses to restrict and focus the overall search space of test pattern generation. The experimental results demonstrate the effectiveness of these learning techniques.

Improving Test Pattern Generation with Implication Learning

Abstract Nowadays SAT algorithms allow larger problem instances to be solved in application domains such as automatic test pattern generation (ATPG) that can also be viewed as solving a SAT problem. The key to a SAT-solver can be scalable is that it is able to take into account the information of high-level structure of formulas. This paper further improves to SAT-based ATPG by analyzing specific structure of circuit instances. This analysis is called heuristic learning where correlations among signals have been established by simple and efficient methods. It is achieved by finding more necessary signal line assignments, by detecting conflicts earlier, and by avoiding unnecessary work during test generation. Among others things, it combines strengths of binary decision graphs (BDD) and SAT techniques to improve the efficiency of test generation. Reconvergent fanout is a fundamental cause of the difficulty in testing circuits, because they introduce dependencies in the values that can be assigned to nodes. This paper exploits reconvergent fanout analysis of circuit to gather information about local signal correlation through BDD learning, and then used the learned information in the conjunctive normal form clauses to restrict and focus the overall search space of test pattern generation. The experimental results demonstrate the effectiveness of these learning techniques.

On Acceleration of SAT-Based ATPG for Industrial Designs

Due to the rapidly growing size of integrated circuits, there is a need for new algorithms for automatic test pattern generation (ATPG). While classical algorithms reach their limit, there have been recent advances in algorithms to solve Boolean Satisfiability (SAT). Because Boolean SAT solvers are working on conjunctive normal forms (CNFs), the problem has to be transformed. During transformation, relevant information about the problem might get lost and, therefore, is not available in the solving process. In this paper, we present a technique that applies structural knowledge about the circuit during the transformation. As a result, the size of the problem instances decreases, as well as the run time of the ATPG process. The technique was implemented, and experimental results are presented. The approach was combined with the ATPG framework of NXP Semiconductors. It is shown that the overall performance of an industrial framework can significantly be improved. Further experiments show the benefits with regard to the efficiency and robustness of the combined approach.

SAT-based ATPG using multilevel compatible don't-cares

In a typical IC design flow, circuits are optimized using multilevel don't cares. The computed don't cares are discarded before Technology Mapping or Automatic Test Pattern Generation (ATPG). In this paper, we present two combinational ATPG algorithms for combinational designs. These algorithms utilize the multilevel don't cares that are computed for the design during technology independent logic optimization. They are based on Boolean Satisfiability (SAT), and utilize the single stuck-at fault model. Both algorithms make use of the Compatible Observability Don't Cares (CODCs) associated with nodes of the circuit, to speed up the ATPG process. For large circuits, both algorithms make use of approximate CODCs (ACODCs), which we can compute efficiently. Our first technique speeds up fault propagation by modifying the active clauses in the transitive fanout (TFO) of the fault site. In our second technique, we define new j - active variables for specific nodes in the transitive fanin (TFI) of the fault site. Using these j-active variables we write additional clauses to speed up fault justification. Experimental results demonstrate that the combination of these techniques (when using CODCs) results in an average reduction of 45% in ATPG runtimes. When ACODCs are used, a speed-up of about 30% is obtained in the ATPG run-times for large designs. We compare our method against a commercial structural ATPG tool as well. Our method is slower for small designs, but for large designs, we obtain a 31% average speedup over the commercial tool.

IGRAINE-an Implication GRaph-bAsed engINE for fast implication, justification, and propagation

Implication, justification, and propagation are three important Boolean problems that have to be solved during many tasks in electronic design automation (EDA) for digital circuits. As they constitute the key components of automatic test pattern generation (ATPG) most algorithms that tackle these problems originate in ATPG research. Due to their fundamental nature these ATPG-based methods have successfully been adopted by logic synthesis and formal verification where they have helped advance the fields of netlist optimization and Boolean equivalence checking. Despite their high importance and wide applicability, the data structures and algorithms suggested so far have proven to be suboptimal and inflexible in several respects. Therefore, we propose IGRAINE, a fast and flexible engine for performing implication, justification, and propagation in combinational circuits that is specifically optimized with respect to these tasks. Due to its modular design, IGRAINE is easily included into new applications that require ATPG-based methods. Our approach is based on a new implication graph (IG) model which forms the core of IGRAINE. Contrary to other IG models, the proposed IG represents all information on the implemented logic function as well as the topology of a combinational circuit in a single graph model. In order to demonstrate the performance of the presented IG-based algorithms for implication, justification, and propagation, we provide experimental results for stuck-at and path delay fault ATPG as well as Boolean equivalence checking. They show that TIP outperforms the state-of-the-art in SAT-based and structure-based ATPG. A comparison with tools for Boolean equivalence checking demonstrates the high effectiveness of our approach.