SAR ADC Research Articles

A Three-Stage Dynamic Comparator for SAR ADC Optimized for Reduced Kickback Noise and Ultra-Low Delay

This paper presents a novel footless single clock-phase three-stage comparator with internally generated regenerative voltage signals for low kickback noise and high speed. The preamplifier and clocked latch topology of dynamic comparators are considered in this brief. The proposed design has been compared by analyzing and optimizing three state-of-the-art comparator designs: Modified StrongARM, Miyahara’s and Three-Stage. These designs are simulated using the 40[Formula: see text]nm CMOS technology process. The area of the proposed comparator is 28.025[Formula: see text][Formula: see text]m2. When simulated in the SPICE-based simulator HSPICE, under typical performance conditions of 0.9[Formula: see text]V supply voltage, 25∘C, 1 GHz operational frequency, typical process corner (tt), and 1[Formula: see text]mV differential voltage, the proposed comparator produces the best post-layout results, with a minimum delay of 59.9[Formula: see text]ps from meta-stability analysis, energy per comparison of 0.175[Formula: see text]pJ/comparison and a kickback noise of 44.55 [Formula: see text]A. The proposed design also shows a significant improvement in the measured performance parameters over the other state-of-the-art dynamic comparators that have been discussed in this brief. The obtained results show that the proposed comparator is appropriate for 12-bit Successive Approximation Resister Analog-to-Digital Converters (SAR-ADCs) in IoT applications.

A Cryo-CMOS 10-bit 60-MS/s SAR ADC with common-mode variation suppression switching scheme and gain boosting dynamic comparator

This paper presents a 10-bit 60-MS/s SAR ADC using an energy-efficient common-mode variation suppression (CMVS) switching scheme. The proposed CMVS switching scheme reduces energy consumption by about 92 % compared to the conventional scheme. Also, it narrows the common-mode variation to 16.6 % VDD. It improves the accuracy of the SAR ADC and makes the comparator and SAR ADC operate at the best-performance region. The proposed comparator adopts a gain boosting dynamic capacitive pre-amplifier to enhance the amplification and accelerate the comparison speed. The regeneration latch keeps the cross-coupled inverter structure to ensure high-speed regeneration. The input pair of the latch suppresses the through current while decreasing the regeneration speed. Therefore, an auxiliary input pair is added to enhance the regeneration speed. The SAR ADC is designed and simulated using 65-nm Cryo-CMOS technology with VDD = 1.2 V. At T = 300 K, it achieves a FoM of 15.39 fJ/conversion-step with 55-MS/s. At T = 4 K, it achieves a FoM of 14.15 fJ/conversion-step with 60-MS/s.

A 10 MHz‐BW 85 dB‐SNDR 4th‐order sturdy MASH 2‐0 noise shaping SAR ADC with 2nd‐order gain‐error‐shaping technique

AbstractThe multi‐stage noise shaping (MASH) ΣΔ ADC has a good potential to achieve high‐order noise shaping (NS) and high resolution. However, it suffers from quantization noise leakage caused by the mismatch between the analogue NS filter and the digital cancellation filter, which greatly degrades the ADC performance. The sturdy MASH topology of the ΣΔ ADC can solve the leakage issue, but it cannot be implemented using the NS SAR ADC due to structural limitations. This paper proposes a sturdy MASH 2‐0 NS SAR to solve the noise leakage issue. The 4th‐order NS is achieved by only using a 2‐0 topology, which is hardware efficient. Instead of eliminating the first‐stage quantization error, the proposed sturdy MASH 2‐0 NS SAR shapes it, achieving better robustness to PVT variables. Furthermore, owing to the first‐stage 2nd‐order NS capability, the impairments of the residue amplifier, including the gain error and nonlinearity, are 2nd‐order shaped. The proposed 4th‐order sturdy MASH 2‐0 NS SAR is implemented in a 28 nm CMOS process, which achieves a SNDR of 85.6 dB and a SFDR of 101.3 dB with 10 MHz BW at OSR of 10, resulting in a Schreier FoM of 178.8 dB/179.4 dB (in SNDR/DR) with power consumption of 4.8 mW.

An 8-MS/s 16-bit SAR ADC With Symmetric Complementary Switching and Split Passive Reference Segmentation in 180-nm Process

An 8-MS/s 16-bit SAR ADC With Symmetric Complementary Switching and Split Passive Reference Segmentation in 180-nm Process

A Low-Power, High-Resolution Analog Front-End Circuit for Carbon-Based SWIR Photodetector

Carbon nanotube field-effect transistors (CNT-FETs) have shown great promise in infrared image detection due to their high mobility, low cost, and compatibility with silicon-based technologies. This paper presents the design and simulation of a column-level analog front-end (AFE) circuit tailored for carbon-based short-wave infrared (SWIR) photodetectors. The AFE integrates a Capacitor Trans-impedance Amplifier (CTIA) for current-to-voltage conversion, coupled with Correlated Double Sampling (CDS) for noise reduction and operational amplifier offset suppression. A 10-bit/125 kHz Successive Approximation analog-to-digital converter (SAR ADC) completes the signal processing chain, achieving rail-to-rail input/output with minimized component count. Fabricated using 0.18 μm CMOS technology, the AFE demonstrates a high signal-to-noise ratio (SNR) of 59.27 dB and an Effective Number of Bits (ENOB) of 9.35, with a detectable current range from 500 pA to 100.5 nA and a total power consumption of 7.5 mW. These results confirm the suitability of the proposed AFE for high-precision, low-power SWIR detection systems, with potential applications in medical imaging, night vision, and autonomous driving systems.

A common-mode insensitive thyristor-based latch regenerative comparator for low supply voltage applications

Presented in this article is a new two-stage rail-to-rail regenerative comparator circuit designed for low supply voltage applications. This work introduces a thyristor-based latch for the first time, allowing the comparator to operate from rail-to-rail inputs. The proposed comparator has been post-layout simulated using a standard 65 nm CMOS technology. The worst-case simulation results demonstrate that the comparator exhibits a delay of less than 22ns and consumes only 132 nW of power at a supply voltage of 0.6V and a sample rate of 1 MHz across its full common-mode range. Furthermore, the total input-referred offset voltage (3std + mean) remains below 21 mV throughout the entire rail-to-rail common-mode voltage range. Compared to the conventional single-stage comparator, the proposed circuit showcases an improvement of over 87 % in terms of delay and energy efficiency. Given its dignified performance metrics, this comparator is well-suited for use in low supply voltage applications such as biomedical implants, successive approximation registers analog-to-digital converters (SAR ADCs), Internet of Things (IoT).

A 16-bit 4-MS/s SAR ADC With Dual-Segmental Bit Weight Self-Calibration

A 16-bit 4-MS/s SAR ADC With Dual-Segmental Bit Weight Self-Calibration

Design of a 0.2V 2.08nW 10-bit 1kS/s High Energy Efficiency SAR ADC with Dummy Capacitor Splitting Technique for Biomedical Applications

Design of a 0.2V 2.08nW 10-bit 1kS/s High Energy Efficiency SAR ADC with Dummy Capacitor Splitting Technique for Biomedical Applications

A 12-bit 50MS/s SAR ADC with non-binary split capacitive DAC in 40nm CMOS

A 12-bit 50MS/s SAR ADC with non-binary split capacitive DAC in 40nm CMOS

Design and Analysis of a Power-Efficient Dynamic Comparator with an Improved Transconductance in Ultra-low Power SAR ADC Applications

Design and Analysis of a Power-Efficient Dynamic Comparator with an Improved Transconductance in Ultra-low Power SAR ADC Applications

An improved kT/C noise cancellation technique with presampling for high‐speed SAR ADCs

AbstractThe kT/C noise cancellation technique can effectively reduce the digital‐to‐analog converter (DAC) size for successive approximation register ADCs and thus relax the burden for input drivers and reference buffers. However, the prior kT/C noise cancellation technique suffers from a hard trade‐off between the noise, amplifier bandwidth and linearity. Here, an improved kT/C noise cancellation technique is proposed to break the trade‐off. It uses presampling to hold the input signal unchanged during the noise cancelling phase, leading to significantly relaxed requirements on the bandwidth and linearity of the amplifier. The proposed technique is verified in a 14‐bit 200 MS/s SAR analog‐to‐digital converter (ADC) with a DAC size of 128 fF. Simulation results show that this work achieves 75.6 dB signal to noise and distortion ratio and consumes 1.56 mW power.

A 18-bit 1-MS/s fully-differential SAR ADC with digital calibration achieving 96.1 dB SNDR

This paper presents a 18-bit 1 MS/s fully-differential Successive-Approximation-Register Analog-to-Digital Converter (SAR ADC) achieving an ENOB of 15.7-bit. To achieve higher performance, a differential DAC utilizing both split and monotonic switching timing is designed. For both dynamic and static performance improvement, five techniques are proposed. First, a foreground digital self-calibration method based on normalized-full-scale-referencing is described to eliminate the capacitor mismatch errors. L-segment capacitors are utilized to measure and calculate the bit weights of other capacitors. Second, a DNL enhancement technique is presented. The fractional capacitors are used to subtract an analog voltage from the DAC before the conversion is finished, which further improve the ADC performance. Third, an adaptive-tracking-extra-bit-trail together with comparator noise extraction and correction for further accuracy enhancement is proposed. Forth, a harmonic calibration technique, which can efficiently attenuate 2-order and 3-order harmonic is introduced. Fifth, a comparator with ultra-low noise and offset is designed to meet the 18-bit 1-MS/s ADC. The ADC is fabricated in a 0.18-μm 5-V CMOS process. It measures a 96.1 dB SNDR and a 110.7 dB SFDR. The DNL and INL are within ±0.32 LSB and ±0.5 LSB, respectively. The overall power consumption of ADC core, drawn from the 5 V power supply, is 45 mW.

A Non-Linear Successive Approximation Finite State Machine for ADCs with Robust Performance

This work presents the detailed design of a Successive Approximation Analog to Digital Data Converter (SAR ADC) using bulk 180 nm CMOS IC technology. The focus of the study is on replacing the typical Successive Approximation Register array with a Finite State Machine. This converter features a fully differential and bipolar architecture, which leads to the logic SAR nonlinear behavior. A novel digital control logic mitigates the conversion errors through the conditions in the previous logic states. The logic scheme, in combination with a robust continuous comparator, demonstrates tolerance to Process, Voltage, and Temperature variations. The architecture does not include calibration or additional redundancies in post-layout simulations to emphasize the exclusive benefits of the new SAR logic. The proposed SAR ADC achieves a 14.07 effective number of bits with 7.04 fJ/conversion step Walden figure of merit in biomedical applications.

A 200kHz-bandwidth 101dB SNDR noise-shaping SAR ADC with NTF strengthening method

A 200kHz-bandwidth 101dB SNDR noise-shaping SAR ADC with NTF strengthening method

A second-order CIFF noise-shaping SAR ADC reusing a dynamic amplifier

A second-order CIFF noise-shaping SAR ADC reusing a dynamic amplifier

Design and Verification of a SAR ADC SystemVerilog Real Number Model

Design and Verification of a SAR ADC SystemVerilog Real Number Model

A 10-bit 40MS/s SAR ADC with a low-noise low-offset dynamic comparator and a high-linearity sampling switch

A 10-bit 40MS/s SAR ADC with a low-noise low-offset dynamic comparator and a high-linearity sampling switch

Input currents of CMOS SAR ADC in microcontroller, their measurement and behavior model from users point of view

The article introduces the possible issue of internal CMOS Successive Approximation Register microcontroller’s Analog-to-Digital Converters (ADC) input currents. It describes the nature of the ADC input current and its dependence on the sampling frequency but also explains the issue when the ADC input appears to the user as a voltage source. Methods for measurement of parameters such as input charge, residual voltage, and equivalent capacitance of sample-hold circuits are presented and used in the proposed simplified model of ADC input behavior. These parameters, which are not listed in the datasheets, if not respected in the data acquisition design, can adversely affect how the ADC is used when measuring signal sources with non-negligible internal resistance. The article also explains how to solve a voltage measurement on a source with high internal resistance even in a situation where, according to datasheets, it should already have limitations. If the microcontroller contains a dynamically switched multiplexer, it can lead to other consequences, such as changing the input current or residual voltage. The proposed simplified CMOS SAR ADC input behavior model in an MCU can help users in an MCU-based data acquisition system design.

A 2.3-5.7 μW Tri-Modal Self-Adaptive Photoplethysmography Sensor Interface IC for Heart Rate, SpO2, and Pulse Transit Time Co-Monitoring.

This paper presents a tri-modal self-adaptive photoplethysmography (PPG) sensor interface IC for concurrently monitoring heart rate, SpO2, and pulse transit time, which is a critical intermediate parameter to derive blood pressure. By implementing a highly-reconfigurable analog front-end (AFE) architecture, flexible signal chain timing control, and flexible dual-LED drivers, this sensor interface provides wide operating space to support various PPG-sensing use cases. A heart-beat-locked-loop (HBLL) scheme is further extended to achieve time-multiplexed dual-input pulse transit time extraction based on two PPG sensors placed at fingertip and chest. A self-adaptive calibration scheme is proposed to automatically match the chip's operating point with the current use case, guaranteeing a sufficient signal-to-noise ratio for the user while consuming minimum system power. This paper proposes a DC offset cancellation (DCOC) approach comprised by a logarithmic transimpedance amplifier and an 8-bit SAR ADC, achieving a measured 38 nA residue error and 8.84 μA maximum input current. Fabricated in a 65nm CMOS process, the proposed tri-modal PPG sensor interface consumes 2.3-5.7 μW AFE power and 1.52 mm2 die area with 102dB (SpO2 mode), 110-116 dB (HR & PTT mode) dynamic range. A SpO2 test case and a HR & PTT test case are both demonstrated in the paper, achieving 18.9 μW and 43.7 μW system power, respectively.

Analysis and Calibration of Bit Weights in SAR and Pipelined SAR ADCs Based on Code Distribution

Analysis and Calibration of Bit Weights in SAR and Pipelined SAR ADCs Based on Code Distribution