RTOS Kernel Research Articles

Static analysis for detecting high-level races in RTOS kernels

We propose a static analysis based approach for detecting high-level races in RTOS kernels popularly used in safety-critical embedded software. High-Level races are indicators of atomicity violations and can lead to erroneous software behaviour with serious consequences. Hitherto techniques for detecting high-level races have relied on model-checking approaches, which are inefficient and apriori unsound. In contrast we propose a technique based on static analysis that is both efficient and sound. The technique is based on the notion of disjoint blocks recently introduced in Chopra et al. (In: Proceedings of 28th European symposium on programming (ESOP), Prague, Czech Republic. LNCS, vol 11423, pp 1–27. Springer, 2019). We evaluate our technique on four popular RTOS kernels and show that it is effective in detecting races, many of them harmful, with a high rate of precision.

Design and Analysis of RTOs based Reconfigurable Cots Design on FPGA

Background:Due to greater potentialto accelerate a wide variety of application, reconfigurable FPGA has become a subject to great deal of research. The FPGA has ability to perform computations in hardware to increase the system performance, while retaining much of the flexibility of software solutions. In recent development, the real-time embedded system are increasingly being built with COTS components namely mass-produced peripherals and by reducing cost through buses and performance improvement. But the available COTS systems do not guarantee any timeliness and do not implement any priority scheduling mechanism. Methods/Statistical Analysis: This article deals with a new approach to create an RTOS based reconfigurable COTS design for FPGA platform. Thereby RTOS kernel is designed for FPGA and COTS system designed on the FPGA. Application/Improvements: At runtime, the hardware tasks are scheduled and allocated system resources like I/O, memory, etc. to successfully export multiple virtual devices for a single physical device. Keywords: FPGA, RTOS based Reconfigurable Commercial-off-the-Shelf

Performance analysis of non-PC/SC based mini-WiMAX connection manager

In order to provide WiMAX network services to specific purposed devices such as credit card systems and surveillance systems, we have proposed a new non-PC/SC based mini WiMAX Connection Manager (non-PC/SC m-WCM) that can be applied to small hardware system or architecture with Micro Controller Unit (MCU). The existing legacy WiMAX Connection Managers (WCMs) generally run on the operating systems such as Windows and Linux. This makes it hard to design and implement lightweight WCMs for the specific purposed devices that have very limited hardware capabilities. In order to solve the problem, we propose a new non-PC/SC m-WCM architecture which has almost same functionalities of the legacy WCM and implement non-PC/SC m-WCM without the performance degradations. The proposed non-PC/SC m-WCM mainly consists of three units; WiMAX module Control Unit (WCU), Data Surveillance Unit (DSU), and External device Program Unit (EPU). Besides these, it also has TCP/IP protocol stack and RTOS kernel, and can transmit date between external end user's device and remote server system over the WiMAX networks. For the delay and throughput performance comparisons with the legacy WCMs, we have implemented the non-PC/SC m-WCM and tested it under a commercial mobile WiMAX network environment. From the experimental results, the non-PC/SC m-WCM is verified to show almost equal stability and delay performances with the legacy WCM and xDSL, but especially better than WCDMA. In the throughput tests, it has been shown that each of the modems shows almost similar throughput performance. Although the proposed WCM is designed with the very limited hardware specifications, it shows no performance degradations compared to the legacy WCMs. As a result, it has a strong possibility to be able to apply the non-PC/SC m-WCM to various types of specific purposed embedded systems, and to provide them with the same levels of WiMAX network services as those provided by the legacy WCMs.

Design and implementation of tiny-WiMAX connection manager (t-WCM) for specific purposed devices

WiMAX network services cannot generally be provided for special purpose devices such as credit card systems and surveillance systems since they are designed to operate only with WCM which should be installed on personal computer/smart card (PC/SC) with Windows platform. In this paper, we propose a design and implementation technique called tiny-WiMAX connection manager (t-WCM) for non-PC/SC WCM to provide WiMAX services to special purpose devices. The t-WCM is composed mainly of three units; WiMAX module control unit (WCU), data surveillance unit (DSU), and external device program unit (EPU). It also has TCP/IP protocol stack and RTOS kernel, and performs data transmission between external end user's device and remote server system over WiMAX networks. For the performance evaluation of the proposed t-WCM, we have implemented the t-WCM and tested it under a commercial mobile WiMAX network environment. From the experimental results, the t-WCM is verified to show almost equal stability and delay performances with the legacy WCM and xDSL, and especially better than 1xEV-DO. As a result, it has a strong possibility to apply the t-WCM to many types of special purpose embedded systems, and consequently to provide various WiMAX network services to them.

Space-Optimal, Wait-Free Real-Time Synchronization

We consider wait-free synchronization for the single-writer/multiple-reader problem in small-memory embedded real-time systems. We present an analytical solution to the problem of determining the minimum, optimal space cost required for this problem, considering a priori knowledge of interferences $the first such result. We also show that the space costs required by previous algorithms can be obtained by our analytical solution, which subsumes them as special cases. We also present a wait-free protocol that utilizes the minimum space cost determined by our analytical solution. Our evaluation studies and implementation measurements using the SHaRK RTOS kernel validate our analytical results

Design-time application mapping and platform exploration for MP-SoC customised run-time management

In an Multi-Processor system-on-Chip (MP-SoC) environment, a customized run-time management layer should be incorporated on top of the basic Operating System services to alleviate the run-time decision-making and to globally optimise costs (e.g. energy consumption) across all active applications, according to application constraints (e.g. performance, user requirements) and available platform resources. To that end, to avoid conservative worst-case assumptions, while also eliminating large run-time overheads on the state-of-the-art RTOS kernels, a Pareto-based approach is proposed combining a design-time application and platform exploration with a low-complexity run-time manager. The design-time exploration phase of this approach is the main contribution of this work. It is also substantiated with two real-life applications (image processing and video codec multimedia). These are simulated on MP-SoC platform simulator and used to illustrate the optimal trade-offs offered by the design-time exploration to the run-time manager.

A scalable single-chip multi-processor architecture with on-chip RTOS kernel

Now that system-on-chip technology is emerging, single-chip multi-processors are becoming feasible. A key problem of designing such systems is the complexity of their on-chip interconnects and memory architecture. It is furthermore unclear at what level software should be integrated. An example of a single-chip multi-processor for real-time (networked) embedded systems is the multi-microprocessor (MµP). Its architecture consists of a scalable number of identical master processors and a configurable set of shared co-processors. Additionally, an on-chip real-time operating system kernel is included to support transparent multi-tasking over the set of master processors. In this paper, we explore the main design issues of the architecture platform on which the MµP is based. In addition, synthesis results are presented for a lightweight configuration of this architecture platform.