Row-column Decomposition Research Articles

Discrete-time distributed algorithms for solving linear equations via layered coordination

This paper is concerned with the problem of designing discrete-time distributed algorithms for solving large-scale linear equations via layered coordination. A row-column decomposition and a column-row decomposition are provided to partition the augmented matrix associated with the linear equations into several block matrices, respectively. By assigning an equation solver layer to computation and a data integration layer to data exchanges, a row-column decomposition-based discrete-time distributed algorithm and a column-row decomposition-based discrete-time distributed algorithm are proposed for solving large-scale linear equations, respectively. It is shown that the distributed algorithms proposed can reach a consensus exponentially on one of the solutions of linear equations. Finally, the effectiveness of the distributed algorithms proposed is validated via the numerical simulation of the power flow calculation of power systems and the problem of solving the large-scale linear equations.

ARCHITECTURAL DESIGN AND OPTIMIZATION OF DISTRIBUTED ARITHMETIC BASED 2-D DISCRETE COSINE TRANSFORM

DCT is immensely used in Multimedia applications because it provides high energy compaction. The proposed architectural design of 1D-DCT employs an efficient computational technique, Distributed arithmetic and is synthesized using front end VLSI technique. The motive of utilising Distributed arithmetic is to have multiplier-less architecture that reduces the Area-delay product in comparison to the multiplier-based design by retaining the same structural regularities. The symmetric property of the DCT kernel matrix is applied to develop the proposed architecture which reduces the requirements of a number of multiplications by almost 50%. The 1D-DCT architecture is extended to 2D-DCT using only N 1D-DCT modules, while the conventional row-column decomposition method requires 2N 1D-DCT modules. The proposed 2D-DCT architecture is designed and implemented on a 65nm LX110T device of Vertex-5 FPGA and its performance evaluation is carried out. The debug and verification process has been carried out using the Virtual input-output technique. The results show improvement in delay and area consumption in contrast with existing models.

A Low Area Fully Pipelined Implementation of JPEG on FPGA

This paper presents a low-area and high-throughput design and implementation of JPEG encoder on FPGA. The design consists of three main components: (1) 2-D DCT module, based on the row-column decomposition technique, (2) Quantization in zigzag ordering, based on look-up tables, and (3) Entropy coder, transforming the quantized DCT coefficients into JPEG words. All components are fully pipelined and optimized for FPGA resource utilization. The proposed implementation of JPEG encoder is able to encode 143 and 71 SDTV frames per second with 720x480 gray scale and color pixels per frame, respectively, on Xilinx Spartan 6 FPGA. Moreover, the proposed architecture is capable of encoding at least 53 and 26 HD Ready TV frames per second with 1280x720 gray scale and color pixels per frame, respectively, on this FPGA chip. Thus, the proposed JPEG encoder architecture is well-suited to various image and video compressing applications where performance and area are significantly important.

Research on Image Sparse Transform Based On FPGA

Compressed sensing (CS) theory breaks through the traditional Nyquist sampling theorem for data acquisition. The study object of CS theory is a sparse representation of signals. Here 2-D image sparse transform was achieved based on discrete cosine orthogonal basis and 2-D image compressed storage was realized based on strong real-time FPGA technology. Furthermore,we introduce the 2D-DCT algorithm based on row-column decomposition structure, and emphatically expound the optimization algorithm of 1-D DCT based on FPGA and illustrate the transpose RAM method between two levels 1-D DCT. By comparing image 2D-DCT transformation Based on FPGA and 2D-DCT calculation result in MATLAB environment, the rationality of the proposed algorithm is verified.

FPGA-based ultrasonic energy mapping with source removal method for damage visualization in composite structures

This paper presents the implementation of an ultrasonic energy mapping (UEM) method in a field programmable gate array (FPGA)-based processing board. This method is integrated into an ultrasonic propagation imaging (UPI) system for real-field application. UEM method involves two-dimensional Fourier transform and wavenumber filtering to capture the energy scattering waves. Performing multi-dimensional Fourier transform in FPGA is a challenging task because it cannot fit into a single FPGA chip, and therefore, external memory is required to handle a large amount of data. The row–column decomposition method is used to perform 2D Fourier transform using two DDR3 SDRAM memories. Additionally, a source removal function is added into the system to highlight the damage when high energy at the source location occurs. The UPI system was applied for inspection of a composite wing box with impact damages. The UEM results showed that a damage of 20 × 20 mm2 was detected successfully in the presence of the source inside the scan area. Moreover, the UEM result is produced in less than 5 s for 57,600 points, which is practical for a real-world, non-destructive testing application.

Efficient Systolic Architecture for VLSI Realization of 2-D Hartley-Like Transform

In this paper, we present a composite systolic structure for VLSI realization of two-dimensional (2-D) separable Hartley-like transform (HLT). We have shown that using the separable nature of 2-D HLT, one can compute it in two pipeline stages by row–column decomposition. Besides, we have presented two linear systolic structures for the computation of those two stages and shown that both the types of linear systolic structures can be orthogonally interspersed together to derive a composite structure for 2-D HLT, which does not require any of transposition buffer. The proposed structure provides two benefits: Neither does it require any on-chip memory for transposition of intermediate matrices nor it involves any delay to perform transposition operation. The proposed design for N × N HLT provides a throughput-rate of N HLT coefficients in every cycle, since row and column processing could be performed concurrently for adjacent pairs of input matrices. Unlike the 2-D discrete Fourier transform (DFT) structures, the proposed structure does not require any complex arithmetic operations. It is comprised of 2N2 locally connected simple processing elements (PEs), where each PE consists of one real-value multiplier and one real-value adder. The complete structure, therefore, involves 2N2 multipliers and the same number of adders, while the 2-D DFT of the same size requires 8N2 multipliers and 8N2 adders.

FPGA Architecture for 2D Discrete Fourier Transform Based on 2D Decomposition for Large-sized Data

Applications based on Discrete Fourier Transforms (DFT) are extensively used in various areas of signal and digital image processing. Of particular interest is the two-dimensional (2D) DFT which is more computation- and bandwidth-intensive than the one-dimensional (1D) DFT. Traditionally, a 2D DFT is computed using Row-Column (RC) decomposition, where 1D DFTs are computed along the rows followed by 1D DFTs along the columns. Both application specific and reconfigurable hardware have been used for high-performance implementations of 2D DFT. However, architectures based on RC decomposition are not efficient for large input size data due to memory bandwidth constraints. In this paper, we propose an efficient architecture to implement the 2D DFT for large-sized input data based on a novel 2D decomposition algorithm. This architecture achieves very high throughput by exploiting the inherent parallelism due to the algorithm decomposition and by utilizing the row-wise burst access pattern of the external memory. A high throughput memory interface has been designed to enable maximum utilization of the memory bandwidth. In addition, an automatic system generator is provided for mapping this architecture onto a reconfigurable platform of Xilinx Virtex5 devices. For a 2K×2K input size, the proposed architecture is 1.96x times faster than RC decomposition based implementation under the same memory constraints, and also outperforms other existing implementations.

3-dimensional vector radix FFT algorithm

This paper presented the 3-dimensional vector radix FFT algorithm.Through the method of decimation-in-time to the 3-dimensional signal,the paper deduced the general form of butterfly computation.The comparison result of various 3-dimensional DFT calculation shows that,the 3-dimensional vector radix FFT algorithm is in low-calculation and more efficient even compared to the 3-dimensional row-column decomposition FFT algorithm.

Parallel-pipeline 8/spl times/8 forward 2-D ICT processor chip for image coding

The Integer Cosine Transform (ICT) presents a performance close to Discrete Cosine Transform (DCT) with a reduced computational complexity. The ICT kernel is integer-based, so computation only requires adding and shifting operations. This work presents a parallel-pipelined architecture of an 8/spl times/8 forward two-dimensional (2-D) ICT(10,9,6,2,3,1) processor for image encoding. A fully pipelined row-column decomposition method based on two one-dimensional (1-D) ICTs and a transpose buffer based on D-type flip-flops is used. The main characteristics of 1-D ICT architecture are high throughput, parallel processing, reduced internal storage, and 100% efficiency in computational elements. The arithmetic units are distributed and are made up of adders/subtractors operating at half the frequency of the input data rate. In this transform, the truncation and rounding errors are only introduced at the final normalization stage. The normalization coefficient word length of 18-bit (13-bit effective) has been established using the requirements of IEEE standard 1180-1990 as a reference. The processor has been implemented using standard cell design methodology in 0.35-/spl mu/m CMOS technology, measures 9.3 mm/sup 2/, and contains 12.4 k gates. The maximum frequency is 300 MHz with a latency of 214 cycles (260 cycles with normalization).

New Cost-Effective VLSI Implementation of a 2-D Discrete Cosine Transform and Its Inverse

This paper first reviewed the two-dimensional discrete cosine transform (2-D DCT) and inverse DCT (IDCT) architectures. Then a new VLSI architecture, namely the transpose free row column decomposition method (TF-RCDM), for 2-D DCT/IDCT is proposed. The new RCDM architecture replaces the transpose circuits with permutation networks and parallel memory modules. As results, the timing overhead of I/O operations is eliminated and the hardware complexity is largely reduced. An accuracy testing system is designed to find the optimum word-length parameters. Based on the accuracy testing system, the proposed architecture has achieved the smallest word-length among the reported 2-D DCT architectures. Synthesis results showed that with 0.25-/spl mu/m CMOS technology library, the area was about 1.5 mm/sup 2/ and the speed was about 125 MHz.

An Efficient 2-D DCT/IDCT Core Design Using Cyclic Convolution and Adder-Based Realization

This paper proposes an efficient two-dimensional (2-D) discrete cosine and inverse discrete cosine transform (DCT/IDCT) core design. Adopting the row-column decomposition technique for computing 2-D DCT/IDCT, we formulate the one-dimensional (1-D) DCT/IDCT into cyclic convolution by properly arranging the input sequence, optimize the multiplications based on the concept of common subexpression sharing, and carry out the multiplications through carry-save adders (CSAs). Using cyclic convolution is helpful in exploiting the word-level data sharing in computing different DCT/IDCT outputs. Adopting the common subexpression sharing is beneficial to the bit-level data sharing in computing the outputs. As compared with some existing approaches of realizing DCT/IDCT, the proposed approach can save on average 20%/spl sim/33% in the delay-area product (gate-count * time-unit) based on a 0.35-/spl mu/m CMOS technology under the data word-lengths ranging from 16/spl sim/24 b. Besides, we have also proposed an IP generator for designing the 2-D DCT/IDCT based on the proposed approach. It provides a design-automation environment with parameter configurations in designing a 2-D DCT/IDCT core that is suitable for most image and video compression applications.

Efficient 2D FFT implementation on mediaprocessors

We have developed an efficient implementation to compute the 2D fast Fourier transform (FFT) on a new very long instruction word programmable mediaprocessor. Using instruction-level parallelism and a multimedia instruction set, our radix-4 Cooley–Tukey algorithm optimally maps the FFT computation to the processing resources of the Hitachi/Equator’s MAP mediaprocessor. We have also achieved more efficient data I/O and lower data transfer time compared to traditional implementations by processing several columns in parallel during the column-wise stage of row–column decomposition. We used a programmable direct memory access engine and a double-buffering scheme in the data cache to perform the computation and the data transfer in parallel. Our implementation resulted in 22.4 ms total execution time for a 512 × 512-point 2D complex FFT, which is faster than previous single-chip programmable or dedicated solutions. The implementations on two other mediaprocessors, the TriMedia TM1100 and the BOPS ManArray, illustrate the importance of the instruction set architecture for achieving high performance and the trend of data I/O becoming the limitation on the 2D FFT performance in newer mediaprocessors.

Two-dimensional DCT∕IDCT architecture

A fully parallel architecture for the computation of a two-dimensional (2-D) discrete cosine transform (DCT), based on row-column decomposition is presented. It uses the same one-dimensional (1-D) DCT unit for the row and column computations and (N2+N) registers to perform the transposition. It possesses features of regularity and modularity, and is thus well suited for VLSI implementation. It can be used for the computation of either the forward or the inverse 2-D DCT. Each 1-D DCT unit uses N fully parallel vector inner product (VIP) units. The design of the VIP units is based on a systematic design methodology using radix-2n arithmetic, which allows partitioning of the elements of each vector into small groups. Array multipliers without the final adder are used to produce the different partial product terms. This allows a more efficient use of 4:2 compressors for the accumulation of the products in the intermediate stages and reduces the number of accumulators from N to one. Using this procedure, the 2-D DCT architecture requires less than N2 multipliers (in terms of area occupied) and only 2N adders. It can compute a N×N-point DCT at a rate of one complete transform per N cycles after an appropriate initial delay.

DCT implementation with distributed arithmetic

This paper presents an efficient method for implementing the Discrete Cosine Transform (DCT) with distributed arithmetic. While conventional approaches use the original DCT algorithm or the even-odd frequency decomposition of the DCT algorithm, the proposed architecture uses the recursive DCT algorithm and requires less area than the conventional approaches, regardless of the memory reduction techniques employed in the ROM Accumulators (RACs). An efficient architecture for implementing the scaled DCT with distributed arithmetic is also proposed. The new architecture requires even less area while keeping the same structural regularity for an easy VLSI implementation. A comparison of synthesized DCT processors shows that the proposed method reduces the hardware area of regular and scaled DCT processors by 17 percent and 23 percent, respectively, relative to a conventional design. With the row-column decomposition method, the proposed architectures can be easily extended to compute the two-dimensional DCT required in many image compression applications such as HDTV.

An area efficient DCT architecture for MPEG-2 video encoder

This paper presents an area efficient VLSI architecture of transform coding module for MPEG-2 video encoder. This module consists of 2-D DCT and 2-D IDCT, Q and IQ, and zigzag and alternate scan conversion circuits. Hardware cost and performance of this module are mainly affected by the 2-D DCT and 2-D IDCT. In the proposed architecture, it is shown that a single 1-D DCT/IDCT could take the roles of the 2-D DCT and 2-D IDCT. It is capable of reusing a single 1-D DCT/IDCT four times. It is based on the row-column decomposition technique. It can be achieved through precise timing schedules. Intuitively, three 1-D DCT/IDCT and a matrix transposition memory could be saved as compared to the conventional architectures, which usually use two one-dimensional transforms and transposition memory. Even though there are some extra circuits due to timing controls and processing sequence schedules, this architecture takes about 24% and 50% respectively less area than the architectures published by Miyazaki et al. (1993) and by Matsiu et al. (1994). This design and implementation are applicable to the MPEG-2 video encoder accepting NTSC and PAL image formats in which the number of clocks to be allocated during a macro block period is 1320 for 54 MHz operating clock. To reduce its processing time, the proposed architecture uses a 3-bit serial distributed arithmetic method. As a result, this architecture can be characterized to maximize the utilization of the hardware resources, end can be used for encoders having a similar structure as the MPEC-2 video encoder. It also can be applied to the ASIC chips for multimedia services especially requiring low hardware complexity.

Recursive fast computation of the two-dimensional discrete cosine transform

An efficient algorithm is presented for computing the two-dimensional discrete cosine transform (2-D DCT) whose size is a power of a prime. Based on a generalised 2-D to one-dimensional (1-D) index mapping scheme, the proposed algorithm decomposes the 2-D DCT outputs into three parts. The first part forms a 2D DCT of a smaller size. The remaining outputs are further decomposed into two parts, depending on the summation of their indices. The latter two parts can be reformulated as a set of circular correlation (CC) or skew-circular correlation (SCC) matrix-vector products by utilising the previously addressed maximum coset decomposition. Such a decomposition procedure can be repetitively carried out for the 2-D DCT of the first part, resulting in a sequence of CC and SCC matrix-vector products of various sizes. Employing fast algorithms for the computation of these CC/SCC operations can substantially reduce the numbers of multiplications compared with those of the conventional row-column decomposition approach. In the special case where the data size is a power of two, the proposed algorithm can be further simplified, calling for computations comparable with those of previous works.

A mode-changeable 2-D DCT/IDCT processor for digital VCR

In a digital VCR, the DCT/IDCT is performed by both the 8/spl times/8 mode and the 2/spl times/4/spl times/8 mode to improve the coding efficiency. A new 2-D DCT/IDCT processor which requires minimal hardware overhead for 8/spl times/8/2/spl times/4/spl times/8 mode change for a digital VCR is presented. The proposed DCT/TDCT processor uses a concurrent architecture and executes both the DCT and IDCT with 8/spl times/8 and 2/spl times/4/spl times/8 mode selection. This chip is implemented on the basis of the row-column decomposition scheme. The proposed architecture minimizes the hardware overhead for the 2/spl times/4/spl times/8 mode by sharing the same data path with the 8/spl times/8 mode as much as possible. The proposed architecture also reduces the hardware and the chip size by exploiting the table look-up method instead of the extra multiplication circuits in the weighting coefficients handling. The implemented DCT/IDCT processor satisfies the accuracy specification of digital VCR.

Systolic architecture for inversediscrete cosine transform

The authors present an algorithm and its systolic implementation for computing the 1-D N-point inverse discrete cosine transform (IDCT), where N is a power of two. The architecture requires (N2 – 1)/3 multipliers and can evaluate one N-point IDCT every clock cycle. Owing to the features of regularity and modularity, the architecture is well suited to VLSI implementation. Compared with existing related arrays, the proposed algorithm has a better area-time performance. In addition, it can be extended to implementing the 2-D IDCT based on the row-column decomposition method.

New systolic array implementation of the 2-D discrete cosine transform and its inverse

A new systolic array without matrix transposition hardware is proposed to compute the two-dimensional discrete cosine transform (2-D DCT) based on the row-column decomposition. This architecture uses N/sup 2/ multipliers to evaluate N/spl times/N-point DCTs at a rate of one complete transform per N clock cycles, where N is even. It possesses the features of regularity and modularity, and is thus well suited to VLSI implementation. As compared to existing pipelined regular architectures for the 2-D DCT, the proposed one has better throughput performance, smaller area-time complexity, and lower communication complexity. The new idea for the 2-D DCT is also extended to derive a similar systolic array for the 2-D inverse discrete cosine transform (IDCT). Simulation results demonstrate that the proposed 2-D DCT and IDCT architectures have good fixed-point error performance for both real image and random data. As a consequence, they are useful for applications where very high throughput rates are required. >

Separable two-dimensional recursive digital filters with zero-phase approximation in the passband

A new class of separable two-dimensional IIR filters with zero-phase approximation in the passband is presented. It is based on one-dimensional digital cosine filters employing non-causal allpass structures. Due to design efficiency and row-column decomposition, the implementation offers substantial computational savings.