Routing Tag Research Articles

Fault Tolerant Gamma-Minus Network

In large-scale supercomputers thousands of processors are connected together to their respective memory modules which are controlled by several control units connected in parallel. Large data streams have to be communicated between these processors and memories through interconnection networks. Multistage interconnection network (MIN) is an efficient way to provide these communications at a very reasonable cost. For such large systems MIN employed should be highly reliable and fast to meet the desired specifications of these high speed switch fabrics. In this paper two new architectures of MIN are proposed which are named as fault-tolerant Gamma-Minus (FTGM-1 & FTGM-2) networks. These proposed architectures are multipath MIN with totally disjoint paths and are highly reliable and fault tolerant. The routing algorithm proposed for these structures is simple distance tag routing with non-backtracking which overcomes rerouting overheads and hence improve communication delays. The proposed MIN ensures multiple fault tolerance at each stage including input and output stage with minimal horizontal distance between source node to destination node. For validating the results, a comparison has been presented between existing MINs with these proposed designs. The proposed MINs outperform the existing MIN in terms of reliability, fault tolerance and up to some extent cost as well.

A minimal resource high‐speed routing lookup mechanism for servers with NetFPGAs

AbstractThis paper studies how high‐performance computer servers, equipped with Field‐Programmable Gate Arrays (FPGAs), can perform high‐speed routing. In particular, routing table lookup is considered since it is a key packet processing bottleneck for future routers that need to operate at Petabits‐per‐second. The paper defines and evaluates three routing lookup schemes used by routers/switches, using Xilinx NetFPGA SUME programmable data plane hardware boards. Two existing schemes, namely IP address‐based Longest Prefix Matching and Multi‐Protocol Label Switching tag‐based exact matching are implemented. In addition, the paper presents a new routing scheme called No Lookup Forwarding Scheme (NLFS) that does not use conventional lookup tables. The NLFS approach adds a custom routing tag that does not require any form of (forwarding) table lookup, and independent of the Binary/Ternary Content Associate Memory (CAM) capacity in the switch/router. The experimental results show that the NLFS scheme utilizes less FPGA resources, while reducing packet lookup latency by up to 18% against longest prefix match which is the de facto lookup mechanism used in switches. The key contribution of this work is that it enables the use of NetFPGAs to reduce CAM capacity requirements in switches/routers to help reduce memory costs. The proposed scheme has several use cases, including provision of on‐demand increase of packet routing capacity in data center networks and support for Network Function Virtualization‐based systems.

Network Status Aware Routing in 3D-CGIN

3D-CGIN is a CGIN providing at least 3 disjoint paths between any communicating pair. It uses alternate source for every sender to ensure availability of 3 disjoint paths. 3D-CGIN is compatible with distance tag routing and destination tag routing schemes. These methods prove quite useful in 3D-CGIN. In the presence of faults, the new path is searched from source to destination. In order to tolerate faults, extra processing is required for selection of new path and diverting/resending the packets on that new path. Generally, the extra processing causes increase in processing time or hop count. To gain the advantage of multiple disjoint paths, we must carefully design the routing scheme, such that, it can minimize extra processing while tolerating the faults. We feel that, use of timely updated network status will certainly help in improving the routing. In 3D-CGIN, we introduce such network status aware strategies. This paper introduces two such schemes, which use pre-computing of routing tags. These methods use the network status to avoid paths with faulty nodes. The paper first discusses the routing in Destination Tag and rerouting. The network 3D-CGIN can tolerate a maximum of 6 faults in worst case, due to the additional link at initial stage. In this paper, we emphasis on various routing strategies those can be used with 3D-CGIN architecture to improve the routing.

Method of state code matrixes in the realization of optical switching using Perfect Shuffle

Based on the Left Perfect Shuffle (LPS) optical communication network constructed by cascade multi-stage LPS interconnection, using Looping algorithm, any arbitrary sequence of the input signals can be realized. However, instead of obtaining the simultaneous state codes of the same level node switches through mathematical analytical expressions directly, only routing tags of each channel can be obtained through mathematical analytical expressions so as to draw out topological chart of the network to obtain the state codes implied in the chart. Thus, the states of the switches cannot be directly programmed and controlled by computer in practical application. In this paper, based on the Looping algorithm, a method of stage code matrixes is presented to resolve this problem. By using the method, the simultaneous state codes of the same level’s four node switches can be directly obtained, which is convenient for the computer to provide controlled signals needed to finish the permutation for each node switch. The method of stage code matrixes provides further theoretical basis for the realization of optical switching by integration of Perfect Shuffle and high-speed optical switches.

Design schemes of dynamic rerouting networks with destination tag routing for tolerating faults and preventing collisions

In fault-tolerant multistage interconnection design, the method of providing disjoint paths can tolerate faults, but it is complicated and hard to choose a collision-free path in disjoint paths networks. A network with disjoint paths can concurrently send more identical packets from the source node to increase the arrival ratio or backtrack a packet to the source and take the other disjoint path, but these two methods might increase the collision ratio. In contrast, a dynamic rerouting method finds an alternative path that tolerates faults or prevents collisions. In this paper, we present methods of designing dynamic rerouting networks. This paper presents (1) three design schemes of dynamic rerouting networks to tolerate faults and prevent collisions; (2) design schemes that enable a dynamic rerouting network to use destination tag routing to save hardware cost in switches for computing rerouting tags; (3) a method to prevent a packet from re-encountering the faulty element again after rerouting to reduce the number of rerouting hops and improve the arrival ratio; and (4) simulation results of related dynamic rerouting networks to realize the factors which influence the arrival ratio including the fault tolerant capability and the number of rerouting hops. According to our proposed design schemes and according to our analysis and simulation results, a designer can choose an applicable dynamic rerouting network by using cost-efficient considerations.

RELIABILITY ANALYSIS OF MUX–DEMUX REPLICATED MULTISTAGE INTERCONNECTION NETWORKS

RELIABILITY ANALYSIS OF MUX–DEMUX REPLICATED MULTISTAGE INTERCONNECTION NETWORKS

Baggage handling in an airplane cargo hold: An ergonomic intervention study

Incidence rates of lost time back and shoulder injuries in the airline industry are some of the highest in all of private industry. Commonly, risk factors associated with such injuries include overexertion, repetitive lifting, and awkward postures. These factors are found in combination in the airline baggage handler job. Twelve male subjects performed a simulated baggage handling task in a kneeling posture under a low ceiling, to test the effects on spinal loading, muscle activity, and trunk motion of (1) providing baggage weight information on the routing tag, and (2) an alternative method for handling and stowing bags. Providing weight information did not alter the biomechanical characteristics of the handling exertions in these subjects. However, it was shown to reduce cumulative spinal loading if used to organize stowing of baggage. The alternative stowing method, tipping bags and storing them on their short sides (like books on a shelf), was found to reduce spinal loads and trunk muscle activity. Relevance to industry Airline baggage handler injuries cost millions of dollars, annually. Two low-cost administrative means of changing their working conditions were explored, and showed promise, in terms of reducing biomechanical loads on the baggage handlers when performing some of their most strenuous activities.

Balance routing traffic in Generalized Shuffle-Exchange Network

A methodology is proposed to handle problem that under equiproble address of packet traffic at the input port, Generalized Shuffle-Exchange Network (GSEN) routes traffic unevenly because of the unbalanced routing tags. The idea is to use routing tag according to probability, which can be evaluated by using Moore-Penrose inverse in matrix analysis. An instance is used to illustrate the idea, and the simulation is done to show the improvement in performance issues.

Fault-tolerant gamma interconnection network without backtracking

A no-backtracking gamma interconnection network (NBGIN) is a modified gamma interconnection network (GIN) that can tolerate one switch or link fault without backward packet transmission. Basically, this can be achieved by providing two alternative paths at all intermediate nodes during the progression of routing through carefully designed algorithm. In this work, a destination tag routing named as NB function is designed. With this NB function, a packet can find an alternate path as soon as it encounters a switch or link fault in NBGIN. The major advantage of NBGIN over gamma-induced networks is that there is no rerouting penalty under a fault. In addition, NBGIN processes the characteristics of one-fault tolerance, destination tag routing, and dynamic rerouting. Furthermore, the routing and rerouting path can be simply determined by the destination tag only instead of being computed with the routing tag.

Fault-tolerant gamma interconnection networks by chaining

The authors propose two single-fault-tolerant gamma interconnection networks. The first is a partially chained gamma interconnection network (PCGIN) with two disjoint paths between any source-destination pair. A PCGIN has the characteristics of one fault tolerance and destination tag routing, but backtracking may be necessary when a fault occurs. To eliminate the backtracking penalties of a PCGIN, a fully chained gamma interconnection network (FCGIN); that can at least tolerate one link or switch fault at each stage without backtracking, is also proposed FCGIN has the advantages of destination tag routing, lower hardware costs than a PCGIN, low fault penalty, and strong reroutability.

Dynamic burst transfer time-slot-base network

This article proposes a new high-speed network architecture called dynamic burst transfer time-slot-base network (DBTN). The DBTN network is based on circuit-switched network technology. A routing tag is attached to a burst at an ingress edge node and the burst is self-routed in a DBTN network, the circuit of which is created dynamically by the routing tag. The routing tag, which is called time-slots-relay, consists of link identifiers from the ingress to the egress nodes and is used to create the circuit. Subsequent data is switched over the circuit being created in an on-the-fly fashion. Each link identifier is loaded into the address control memory (ACM) of each circuit switching node, and thereby the circuit to the destination is created dynamically. Subsequent user data follows immediately after the time-slots-relay and is sent over the established circuit. Thus short-lived fairly large data transfers such as WWW traffic are efficiently carried. A circuit between adjacent nodes is created and released dynamically so bandwidth efficiency is improved compared with conventional circuit-switched networks. Time division multiplexing of the circuit-switched network is utilized so there is no delay jitter or loss within a burst. We address the performance of DBTN switches and report the experimental system.

A high-performance ATM switch based on modified shuffle-exchange network

This paper presents an output buffering ATM switch, called modified shuffle-exchange network (MSN) that is obtained by inserting a connection pattern just after every other shuffle-exchange stage. The purpose of modifying a shuffle-exchange network by inserting a connection pattern is to reduce significantly the number of its internal conflicts. Each link of every other stage of MSN has a filter to route successful packets to their destinations. Instead of employing the traditional destination tag routing scheme on MSN, we developed a fast destination tag routing scheme, called FDR, for MSN. In the traditional destination tag routing scheme, the routing tag of a packet is made equal to its destination address. In FDR, however, the routing tag of a packet is determined by its destination address as well as source address. FDR often requires less than log 2 N stages to route a packet from its source to destination, which leads the traffic load to be reduced at the successive stages of the network. An analytical model is presented to analyze the performance of MSN under uniform traffic. Under a variety of traffic models, including uniform, hot-spot, ATM bursty, and output concentration, extensive simulations are run to examine and compare the performance of MSN with two existing similar networks. The simulation results show that MSN with FDR improves the packet loss probability substantially.

Adaptive message routing in a class of fault-tolerant multistage interconnection networks

Multistage interconnection networks (MINs) are often used to provide interconnections in multiprocessor systems. A unique path MIN usually has lower hardware complexity and simple control algorithm, but it lacks fault-tolerance. This paper proposes a class of multipath MINs, which are obtained by adding auxiliary links at the final stage in quad tree networks so that they can provide more paths between each source-destination pair, and presents their routing algorithm which is both destination tag based and adaptive. Starting with the routing tag for the minimum path between a given source-destination pair, the routing algorithm uses a set of rules to select switches and modify routing tag. In addition to trying the auxiliary link when both of the output links are unavailable, the second output link is tried before the auxiliary link when the first output link is unavailable. This feature distinguishes the proposed routing algorithm from the one for quad tree networks and makes better use of all the possible paths between the given source-destination pair. At the end of this paper, an index of performance called capacity is introduced to compare different kinds of MINs. Comparison shows that the proposed MINs have better capacity than quad tree networks.

A three-stage ATM switch with cell-level path allocation

A method is described for performing routing in three-stage asynchronous transfer mode (ATM) switches which feature multiple channels between the switch modules in adjacent stages. The method is suited to hardware implementation using parallelism to achieve a very short execution time. This allows cell-level routing to be performed, whereby routes are updated in each time slot. The algorithm allows a contention-free routing to be performed, so that buffering is not required in the intermediate stage. An algorithm with this property, which preserves the cell sequence, is referred to as a path allocation algorithm. A detailed description of the necessary hardware is presented. This hardware uses a novel circuit to count the number of cells requesting each output module, it allocates a path through the intermediate stage of the switch to each cell, and it generates a routing tag for each cell, indicating the path assigned to it. The method of routing tag assignment described employs a nonblocking copy network. The use of highly parallel hardware reduces the clock rate required of the circuitry, for a given-switch size. The performance of ATM switches using this path allocation algorithm has been evaluated by simulation, and is described.

A kind of Multistage Interconnection Networks with multiple paths

Multistage Interconnection Networks (MINs) are often used to provide interconnections in multiprocessor systems. A unique path MIN usually has lower hardware complexity and a simple control algorithm, but it lacks fault tolerance. This paper proposes a kind of multipath MINs, which are obtained by adding auxiliary links at the final stage in Quad Tree (QT) networks so that they can provide more paths between each source-destination pair, and presents their routing algorithm which is both destination tag based and adaptive. Starting with the routing tag for the minimum path between a given source-destination pair, the routing algorithm uses a set of rules to select switches and modify routing tag. In addition to trying the auxiliary link whenlink 0 andlink 1 are unavailable,link 1 will be tried whenlink 0 is unavailable. This feature distinguishing the proposed routing algorithm from that for QT networks makes better use of all the possible paths between the given source-destination pair. In the end, this paper introduces a performance index, which is calledcapacity, to compare different kinds of MINs. Comparison shows that the proposed MINs have bettercapacity than QT networks.

CGIN: a fault tolerant modified Gamma interconnection network

To improve the terminal reliability of the Gamma interconnection network (GIN), we consider altering its connecting patterns between stages to attain multiple disjoint paths between any source and destination pair. The new modified GIN, referred to as a CGIN with connecting patterns between stages exhibiting a cyclic feature, is able to tolerate any arbitrary single fault and to lift up terminal reliability accordingly. If several rows of switching elements are fabricated in one chip using the VLSI technology, a CGIN could lead to reduced cost because the pin count per chip decreases and the layout area taken by connections shrinks. To make routing and rerouting in the CGIN more efficient and simpler to implement, destination tag routing and rerouting is also provided.

The composite banyan network

A new multipath multistage interconnection network called the composite banyan network is proposed. The network incorporates both the banyan and the reverse banyan networks and is constructed by superimposing the two. The basic building blocks in the composite banyan network are 3/spl times/3 switching elements with log/sub 2/N stages. A major advantage of the composite banyan network over existing networks with 3/spl times/3 SEs is an efficient and fast control algorithm that sets up a path between any source and destination pair. Instead of complex numerical calculations, the network can easily generate a primary routing tag and alternate tags through simple binary operations. Also, the network has a lot of favorable features, including regularity, symmetry, and easy rerouting capability under faults and conflicts. It is shown that at least two totally disjoint paths exist between any source and destination pair, which increase the degree of fault-tolerance. A deterministic permutation routing algorithm is also developed for the 8/spl times/8 composite banyan network, Using a simple tabular method, it is shown that the algorithm always finds a set of conflict-free tags.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Comparison of reconfiguration schemes for the C2SC MIN operating in the broadcast mode

The complementary two-stage cube (C2SC) provides four paths between every source and destination pair so that all single faults and many multiple faults can be tolerated. One of the key issues in multiple-path multistage interconnection networks (MIN's) is the manner in which rerouting is achieved when the network has faults. In this paper, we present four reconfiguration schemes for broadcast connections of the C2SC in the presence of one or multiple faults, and these are: destination discriminator, divide and broadcast, decoded routing tag, and conservative schemes. A hardware implementation and a cost/performance analysis of the four schemes were carried out. The analysis includes comparison of hardware cost, reconfiguration time, cost-reconfiguration time product, and regularity and modularity. The cost/performance analysis and simulation results indicate that the destination discriminator scheme has the lowest cost-reconfiguration time product and has relatively high regularity and modularity.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Routing and path length algorithm for a cost-effective four-tree multistage interconnection network

The characteristics of a new class of irregular fault-tolerant multi-stage interconnection network (MIN) called the four-tree (FT) network are analysed. A FT network can provide ‘full access’ capability even in the presence of multiple faults and is also cost-effective in comparison to other fault tolerant MINs. Rerouting in the presence of faults can be accomplished dynamically without resorting to backtracking. Further, for a non-uniform reference model, the network gives a larger throughput than any regular type of MIN due to smaller path lengths between a processor and its favourite memory modules. Algorithms for computing the path lengths and routing tags are developed for the proposed networks.

Destination tag routing techniques based on a state model for the IADM network

A 'state model' is proposed for solving the problem of routing and rerouting messages in the inverse augmented data manipulator (IADM) network. Necessary and sufficient conditions the reroutability of messages are established using this model, and destination tag schemes are derived. These schemes are simpler, more efficient, and require less complex hardware than previously proposed routing schemes. Two destination tag schemes are proposed. A universal rerouting algorithm is constructed based on one of the schemes. It finds a blockage-free path for any combination of multiple blockages if there exists such a path, and indicates the absence of such a path if there exists none. In addition, the state model is used to derive constructively a lower bound on the number of subgraphs which are isomorphic to the indirect binary n-cube network in the IADM network. This knowledge can be used to characterize properties of the IADM networks and for permutation routing in the IADM networks. >