Routing Lookup Research Articles

Cuckoo Bloom Hybrid Filter: Algorithm and Hardware Architecture for High Performance Satellite Internet Protocol Route Lookup

The next-generation satellite Internet Protocol (IP) router is required to achieve tens of millions of route lookups per second, since satellite Internet services based on low Earth orbit (LEO) constellations have become a reality. Due to the limitation of hardware resources on satellites and the high reliability requirements for equipment, a new satellite IP route lookup architecture is proposed in this paper. The proposed architecture uses a Bloom and cuckoo filter-based structure called cuckoo Bloom hybrid filter (CBHF), which guarantees only one off-chip memory access per lookup, to accelerate the Prefix-Route Trie (PR-Trie) algorithm. The proposed architecture has been evaluated through both a behavioral simulation in C++ language and a hardware implementation in Verilog hardware description language (HDL). Our simulation and implementation results show that the proposed satellite IP route lookup architecture can achieve a single-port throughput beyond 13 Gbps on a field programmable gate array (FPGA) board with a single DDR3 memory chip when operating at 200 MHz. In addition, the resource utilization in the FPGA shows that the proposed architecture also supports triple modular redundancy (TMR) to enhance reliability.

Search mechanism for data contents based on bloom filter and tree hybrid structure in system wide information management

AbstractThe system wide information management (SWIM) system infrastructure layer uses information‐centric networking (ICN) to implement the cache routing and sharing of air traffic information data. The SWIM network searches and forwards routes on the basis of content names. The variable length, hierarchical name structure, and routing updates caused by the frequent publication and deletion of content make the implementation of fast name routing lookup algorithms a significant but arduous task. To address this problem, this study designed a name matching mechanism on the basis of the hybrid structure of the Bloom filter and the Tree. Compared with the traditional Bloom filter search scheme, this search mechanism reduces the quantity of Bloom filter insertion entries and reduces the possibility of hash collisions. Compared with the traditional Tree search scheme, the proposed mechanism can effectively solve the problem of numerous memory accesses caused by extremely long name prefixes, improving the query efficiency. In addition, the proposed composite structure is compared with several methods, such as DIPIT and NPT, by analyzing the effects of layering, global delay and search speed. The experimental results show that the proposed structure has a favourable performance in terms of storage overhead and search speed.

PR-Trie: A Hybrid Trie with Ant Colony Optimization Based Prefix Partitioning for Memory-Efficient IPv4/IPv6 Route Lookup

Memory-efficient Internet Protocol (IP) lookup with high speed is essential to achieve link-speed packet forwarding in IP routers. The rapid growth of Internet traffic and the development of optical link technologies have made IP lookup a major performance bottleneck in core routers. In this paper, we propose a new IP route lookup architecture based on hardware called Prefix-Route Trie (PR-Trie), which supports both IPv4 and IPv6 addresses. In PR-Trie, we develop a novel structure called Overlapping Hybrid Trie (OHT) to perform fast longest-prefix-matching (LPM) based on Multibit-Trie (MT), and a hash-based level matching query used to achieve only one off-chip memory access per lookup. In addition, the proposed PR-Trie also supports fast incremental updates. Since the memory complexity in MT-based IP lookup schemes depends on the level-partitioning solution and the data structure used, we develop an optimization algorithm called Bitmap-based Prefix Partitioning Optimization (BP2O). The proposed BP2O is based on a heuristic search using Ant Colony Optimization (ACO) algorithms to optimize memory efficiency. Experimental results using real-life routing tables prove that our proposal has superior memory efficiency. Theoretical performance analyses show that PR-Trie outperforms the classical Trie-based IP lookup algorithms.

Perfect Hash-Based Routing Lookup for LEO Constellation Backbone Network

The performance of packet forwarding mainly relies on the routing lookup (RL) in high-speed routers and switches. Due to the network topology change and the limited resource on aerospace devices, the RL strategy for LEO constellation backbone networks should be specifically designed. Targeting lower resource consumption, we first propose the perfect hash-based RL, including a Perfect Hash Function (PHF) for metarule space compression plus random access for the output interface. A Satellite Perfect Hash Function (SPHF) algorithm is proposed to generate efficient hash functions with limited storage. For 10000 randomized keys, the SPHF algorithm constructs 50-Kb PHFs in 3.05 milliseconds with 538 Kb storage. Then we design the Routing-oriented Hash Function (RHF) algorithm by fusing the perfect hash and RL, and optimize RHF towards the hardware implementation. The RHF algorithm is robust to different RL scenarios. In the FPGA (xc7k70t-fbv900-1) experiment with 10000 32-bit metarules and 4 output interfaces, a typical RHF algorithm (RHF1) costs only 13.2 ns and 1429 equivalent LUTs to lookup each packet under 312.5 MHz clock frequency. Compared with most advanced Ternary Content Addressable Memory (TCAM) based implementations, RHF1 reduces the storage and logic resources by at least an order of magnitude while keeping comparable lookup latency in the same FPGA Chip. This paper provides a design mentality for the RL of LEO constellation backbone networks.

LPR-Trie: A fast IPv6 routing lookup algorithm with virtual nodes

The number of IPv6 routes in todays backbone routers has grown rapidly, which has put tremendous pressure on route lookup and storage. Based on the analysis of IPv6 address prefix length and distribution characteristics, this paper proposes an IPv6 route lookup architecture called LPR-Trie. The core idea of the algorithm is to utilize more spaces and accelerate routing lookup. Moreover, we put forward the concept of virtual nodes, and leverage the link between virtual nodes and ordinary nodes to accelerate routing lookup. We provide the longest prefix routing entry (LPR) calculation algorithm to achieve the longest prefix match. The experimental results show that the virtual node mechanism increases the search speed up to 244%, and the virtual nodes have better stability by setting an appropriate keep-alive time according to the characteristics of actual traffic. This paper shows that our design improves the routing lookup speed and have better memory utilization.

A minimal resource high‐speed routing lookup mechanism for servers with NetFPGAs

AbstractThis paper studies how high‐performance computer servers, equipped with Field‐Programmable Gate Arrays (FPGAs), can perform high‐speed routing. In particular, routing table lookup is considered since it is a key packet processing bottleneck for future routers that need to operate at Petabits‐per‐second. The paper defines and evaluates three routing lookup schemes used by routers/switches, using Xilinx NetFPGA SUME programmable data plane hardware boards. Two existing schemes, namely IP address‐based Longest Prefix Matching and Multi‐Protocol Label Switching tag‐based exact matching are implemented. In addition, the paper presents a new routing scheme called No Lookup Forwarding Scheme (NLFS) that does not use conventional lookup tables. The NLFS approach adds a custom routing tag that does not require any form of (forwarding) table lookup, and independent of the Binary/Ternary Content Associate Memory (CAM) capacity in the switch/router. The experimental results show that the NLFS scheme utilizes less FPGA resources, while reducing packet lookup latency by up to 18% against longest prefix match which is the de facto lookup mechanism used in switches. The key contribution of this work is that it enables the use of NetFPGAs to reduce CAM capacity requirements in switches/routers to help reduce memory costs. The proposed scheme has several use cases, including provision of on‐demand increase of packet routing capacity in data center networks and support for Network Function Virtualization‐based systems.

Highly Available Packet Buffer Design With Hybrid Nonvolatile Memory

Internet routers/switches are vulnerable to system failures which require a power reset. Tremendous efforts are made to guarantee the high availability of the systems. A recent work shows that a phase change memory (PCM)-based routing lookup table can achieve high availability in the destination lookup of routers/switches. However, a packet buffer in routers/switches cannot benefit from the lookup table approach because it requires a much larger and higher-bandwidth memory system and its memory traffic is equally divided into reads and writes, while routing table accesses are mostly read-dominant. PCM can provide high availability even when the system undergoes a power reset but exhibits unacceptable write bandwidth. In this work, we propose a magnetic RAM (MRAM)/PCM-based hybrid memory packet buffer and a packet mapping method. A small MRAM combined with a large PCM can outperform the dynamic random access memory (DRAM)-based packet buffer by 28.5% or 22.4% on average for internet-mix packet traffic when optimizing only bandwidth or both bandwidth and lifetime. The proposed adaptive packet mapping method maps small packets less than a predetermined packet size threshold to MRAM for maximizing PCM bandwidth as small packets degrade row buffer locality in PCM. In addition, the mapping method dynamically changes the packet size threshold to capture the working set of packet buffering, which significantly improves PCM lifetime.

Mathematical analysis on forwarding information base compression

With the fast development of Internet, the size of routing table in the backbone router continues to grow rapidly. forwarding information base (FIB), which is derived from routing table, is stored in line-card to conduct routing lookup. Since the line-card’s memory is limited, it would be worthwhile to compress the FIB for consuming less storage. Therefore, various FIB compression algorithms have been proposed. However, there is no well-presented mathematical support for the feasibility of the FIB compression solution, nor any mathematical derivation to prove the correctness of these algorithms. To address these problems, we propose a universal mathematical method based on the Group theory. By defining a Group representing the longest prefix matching rule, the bound of the worst case of FIB compression solution can be figured out. Furthermore, in order to guarantee the ultimate correctness of FIB compression algorithms, routing table equation test is proposed and implemented to verify the equivalence of the two routing tables before and after compression by traversing the 32-bit IP address space.

A novel routing algorithm for IoT cloud based on hash offset tree

IoT-Cloud has been played significant role and helped doctors or physicians to add wisdom for healthcare, A data center network (DCN) and a software defined network (SDN) in IoT-Cloud are characterized by a considerable increase in routing table entries, substantial rise in network traffic and higher demands on route forwarding speed. To address these issues, an efficient prefix-matching algorithm that combines the strengths of the hash and Trie methods is proposed to look up and forward the packets more efficiently in the SDN for Healthcare IoT-Cloud. To achieve this objective, the presented study designs a hash offset Trie match on longest prefix (HOTMLP) algorithm. The routing table matching on longest prefix is divided into common prefix match and feature prefix match in this routing algorithm. Common parts of all route prefixes are stored using the hash table to reduce storage space and matching step size. The exact prefix-matching entry is identified using the Trie method. Theoretical analysis demonstrates that the proposed algorithm looks up faster, updates more easily, and stores the data with less space. Achieving the longest prefix match via HOTMLP has a complexity of “O(2+n∕k)”. In the worst case, the largest number of “n” is 8 for the ipv4 address and 32 for the ipv6 address. Experimental results prove that the proposed algorithm is able to meet the requirements of the core route on routing lookup efficiency and forward tens of millions of packets per second.

A Withered Tree Comes to Life Again: Enabling In-Network Caching in the Traditional IP Network

This article presents our work proposing in-network caching in IP-based networks by adding a content identifier into a newly defined IPv6 extension header, where the new architecture is named CAIP. CAIP abandons the complicated name-based forwarding table in ICN, and instead integrates IP routing lookup with cache index lookup, which is compatible with the IP network and also inherits the proven advantages of ICN. Cache index exchanging and cooperative caching are implemented between one-hop CAIP enabled neighboring routers, which is simple but efficient. Moreover, for per-chunk caching, as an extension, bitmap is introduced to merge multiple request packets into one. Performance analysis shows that CAIP gains significant performance improvement in terms of access delay and traffic load.

A Multi-stage IPv6 Routing Lookup Algorithm Based on Hash Table and Multibit Trie

The address length of IPv6 is 128 and it has no classification addressing, which makes routing lookup processing burden of core router is heavier and the requirements are higher. As many existing algorithms cannot adapt to new requirements after expanding to IPv6, it is necessary to propose a new routing lookup algorithm based on IPv6. After thorough analysis of the IPv6 address prefix distribution regularity, this paper proposes a new scheme based on simple data structure: Hash Table and Multibit Trie (retrieval). This algorithm first classifies the prefix value and then starts its first lookup by using the first 48bits prefix of the IPv6 Address. Simulation results show that in most cases, the algorithm needs only one memory access to find the next hop routing information. This algorithm has high lookup speed and can be easily implemented with hardware.

Minnie: An SDN world with few compressed forwarding rules

Software Defined Networking (SDN) is gaining momentum with the support of major manufacturers. While it brings flexibility to the management of flows within the data center fabric, this flexibility comes at the cost of smaller routing table capacities. Indeed, the Ternary Content-Addressable Memory (TCAM) needed by SDN devices has smaller capacities than CAMs used in legacy hardware.In this paper, we investigate compression techniques to maximize the utility of SDN switches forwarding tables. We validate our algorithm, called Minnie, with intensive simulations for well-known data center topologies, to study its efficiency and compression ratio for a large number of forwarding rules. Our results indicate that Minnie scales well, being able to deal with around a million of different flows with less than 1000 forwarding entries per SDN switch, requiring negligible computation time.To assess the operational viability of Minnie in real networks, we deployed a testbed able to emulate a k=4 Fat-Tree data center topology. We demonstrate on the one hand, that even with a small number of clients, the limit in terms of number of rules is reached if no compression is performed, increasing the delay of new incoming flows. Minnie, on the other hand, reduces drastically the number of rules that need to be stored, with no packet losses, nor detectable extra delays if routing lookups are done in the Application-Specific Integrated Circuits (ASICs).Hence, both simulations and experimental results suggest that Minnie can be safely deployed in real networks, providing compression ratios between 70% and 99%.

An SRAM-based novel hardware architecture for longest prefix matching for IP route lookup

A static random access memory (SRAM)-based novel hardware architecture for longest prefix match (LPM) search scheme has been proposed in this paper. The key concept of this architecture is to store the IP prefixes virtually in the forwarding table. This architecture reduces memory consumption by using a two-tier hierarchical SRAM-based memory structure for maintaining the next hop port information. Originally, next hop addresses are kept in the shared global memory called next hop global memory (NHGM) and its links are maintained in another memory, called next hop link memory (NHLM). This approximately reduces memory consumption by 50---62.5% compared to existing SRAM-based schemes. The proposed architecture consumes single memory write cycle to store an IP prefix and also takes single memory read cycle for LPM search. However, finding next hop information incurs two memory read cycles due to hierarchical next hop memory structure. The proposed scheme performs an LPM lookup operation in 1.05---1.31 ns in IPv4 and between 1.05 and 1.6 ns in IPv6. This results into LPM search throughput of 950 million lookups per second (MLPS) to 760 MLPS in IPv4 and between 620 and 950 MLPS in IPv6. The average search throughput achievable from this architecture is roughly 850 MLPS in IPv4 and 780 MLPS in IPv6. The numerical results show that this architecture significantly reduces memory requirement, power consumption, and transistor-count/bit requirement.

A Symmetric Lookup-based Secure P2P Routing Algorithm

To prevent structured peer to peer (P2P) overlay networksfrom being attacked by malicious nodes, a symmetric lookup-based routing algorithm referred to as Symmetric-Chord is proposed in this paper. The proposed algorithm determines the precision of routing lookup by constructing multiple paths to the destination. The selective routing algorithm is used to acquire information on the neighbors of the root. Authenticity of the root is validated via consistency shown between the information ascertained from the neighbors and information from the yet-to-be-verified root, resulting in greater efficiency of resource lookup. Simulation results demonstrate that Symmetric-Chordhas the capability of detecting malicious nodes both accurately and efficiently, so as to identify which root holds the correct key, and provides an effective approach to the routing security for the P2P overlay network.

Evaluation and Comparison of Binary Trie base IP Lookup Algorithms with Real Edge Router IP Prefix Dataset

Internet network is comprised of routers that forward packets towards their destinations. IP routing lookup requires computing the Best-Matching Prefix. The main Functionality of Router is finding the Appropriate Path for Packet. There are many Algorithms for IP-Lookup with different Speed, Complexity and Memory usage. In This Paper Three Binary Trie algorithms will be considered for Performance Analysis. These algorithms are Priority-Trie, Disjoint Binary and Binary Trie. We consider three parameters for comparison, these parameters are Time, Memory and Complexity of Algorithms. For performance analysis, we develop and run algorithms with real Lookup-Tables which were used in an edge router

멀티미디어 인터넷망의 최적화 전송을 위한 라벨링망 응용 정책설정 고찰

ABSTRACT Traditional IP routing, see only the Destination Address When Forwarding Layer 3 routing and exchange information and Destination-Based Routing Lookup is required for all Hop. Thus, all routers Full Internet routing information, the route information of more than about 120,000 may require. Therefore, the router configuration, which can be dispersed in the environment, the traffic load is required in accordance with this congestion. In this study, a unique characteristic of the Internet in the environment of an existing network Best Effect for QoS guarantee and hardware high speed switching of large multimedia data transmitted using a Labeling for forwarding a packet environment configuration is required. Video Stream Broadcast Transport Labeling rather than in much of the higher performance of the multi-step policy to most of the Video Stream Packet deulim was fixed to Labeling Header Format proposes a method of applying an effective QoS policy to a more simplified policy. 키워드 :

Poptrie

Internet of Things leads to routing table explosion. An inexpensive approach for IP routing table lookup is required against ever growing size of the Internet. We contribute by a fast and scalable software routing lookup algorithm based on a multiway trie, called Poptrie. Named after our approach to traversing the tree, it leverages the population count instruction on bit-vector indices for the descendant nodes to compress the data structure within the CPU cache. Poptrie outperforms the state-of-the-art technologies, Tree BitMap, DXR and SAIL, in all of the evaluations using random and real destination queries on 35 routing tables, including the real global tier-1 ISP's full-route routing table. Poptrie peaks between 174 and over 240 Million lookups per second (Mlps) with a single core and tables with 500--800k routes, consistently 4--578% faster than all competing algorithms in all the tests we ran. We provide the comprehensive performance evaluation, remarkably with the CPU cycle analysis. This paper shows the suitability of Poptrie in the future Internet including IPv6, where a larger route table is expected with longer prefixes.

A memory-efficient parallel routing lookup model with fast updates

Routing lookup, as a core function of routers for forwarding and filtering packets, has confronted with serious challenges nowadays, ranging from memory efficiency, update performance and throughput. Rather than seeking optimization techniques for the traditional lookup model, this paper presents a brand-new parallel lookup model, named Split Routing Lookup Model. In consideration of partial similarities among prefixes, we split all prefixes to produce redundancies, which are then removed during information integration. After that, the on-chip structure is compressed sharply. Besides, by such “splitting”, route updates are diverged to be more targeted, and the lookup process is also decomposed to support parallel processing.With 14 real-world routing data, the proposed model is evaluated through 4 classic trie-based approaches, in comparison with their traditional implementations. The encouraging results show the superiorities of the proposed model in a comprehensive view. The on-chip memory savings are up to 99.2% and 94.8% for IPv4/6 respectively. While the reduction of update overhead, even in the worst case, is 50% and 30% respectively. Moreover, the pipeline depth is also reduced by 25–50%. Besides, another 2 techniques are selected to evaluate the proposed model on the virtual router platform. According to the results, based on the proposed model, 160KB on-chip memory is enough to store 14 virtual routers, each consuming only 11KB on average. In this way, the scalability of the proposed model to virtual routers is also clearly demonstrated.

IPv6 routing table lookup algorithm based on multi-layer hybrid structure

Most of the existing routing lookup algorithms usually use a variety of optimization methods to improve search performance;however they need to reconstruct the entire routing table to update routing information.Concerning this,a multi-layer hybrid structure algorithm for IPv6 routing table lookup was proposed.The first layer used the advantage of the optimal search tree for reference.The different values of prefix 1-16 bit were ordered by their probability of occurrence in the routing table,and were stored in the linear list.The 17-32 bit and 33-48 bit of prefix were organized respectively with the balanced binary tree.The 49~64 bit of prefix was organized with the linear list.The evaluation results show that the proposed scheme performs faster,occupies less memory,and supports incremental update.

Low Leakage TCAM for IP Lookup Using Two-Side Self-Gating

Ternary content-addressable memory (TCAM) is a popular hardware device for fast routing lookup and an attractive solution for applications such as packet forwarding and classification. However, the high cost and power consumption are limiting its popularity and versatility. In this paper, a low leakage power TCAM architecture which uses two-side self power gating technique is proposed to reduce the leakage power dissipation of the mask SRAM cells. The TCAM mask cells are divided into several segments, and the mask bits of one segment are the same except for the boundary segment. In this design, the boundary segment is activated and the others are disabled so that the leakage power can be reduced. The experimental results show that average 26% leakage power can be reduced by using UMC 90 nm CMOS process with 1.0 V supply voltage when compared with the traditional TCAM architecture.