Round-robin Order Research Articles

Scheduling configuration memory error checks to improve the reliability of FPGA‐based systems

Field-programmable gate arrays are susceptible to radiation-induced single event upsets. These are commonly dealt with using triple modular redundancy (TMR) and module-based configuration memory error recovery (MER). By triplicating components and voting on their outputs, TMR helps localise configuration memory errors, and by reconfiguring faulty components, MER swiftly corrects them. However, the order in which TMR voters are checked inevitably impacts the overall system reliability. In this study, the authors outline an approach for computing the reliability of TMR–MER systems that consist of finitely many components. They demonstrate that system reliability is improved when the more vulnerable components are checked more frequently than when they are checked in round-robin order. They propose a genetic algorithm for finding a voter checking schedule that maximises the reliability of TMR–MER systems. Results indicate that the mean time to failure (MTTF) of these systems can be increased by up to 400% when variable-rate voter checking (VRVC) is used instead of round robin. They show that VRVC achieves 15–23% increase in MTTF with a 10× reduction in checking frequency to reduce system power. They also found that VRVC detects errors 44% faster on average than round robin.

A multiagent, dynamic rank-driven multi-deme architecture for real-valued multiobjective optimization

Multiobjective real parameter optimization is a challenging problem in majority of engineering applications. This paper presents a creative multiagent and dynamic multi-deme architecture based on a novel collaboration mechanism for the solution of multiobjective real-parameter optimization problems. The proposed architecture comprises a number of multiobjective metaheuristic agents that act on subsets of a population based on a cyclic assignment order. The proposed multiagent architecture works iteratively in sessions including two consecutive phases: in the first phase, a population of solutions is divided into subpopulations based on dominance ranks of its elements. In the second phase, each multiobjective metaheuristic is assigned to work on a subpopulation based on a cyclic or round-robin order. Hence, each metaheuristic operates on a different-rank subpopulation in subsequent sessions, where a session starts with a new assignment of metaheuristics and ends when termination criteria for the session are satisfied. Individual agents have their local archives of non-dominated solutions extracted in a session, while there is a global archive keeping all non-dominated solutions found so far. At the end of each session, all subpopulations are combined into one global population to be used for the initialization of the next session. Similarly, all local archives are merged with the global archive to get the set of all non-dominated solutions found by all metaheuristics through working on subsets of different rank-levels. This way, the metaheuristics cooperate with each other by sharing their search experiences through collecting them in a common population and a common global archive. The proposed multiagent system is experimentally evaluated using the well-known CEC2009 multiobjective optimization benchmark problems set. Analysis of the experimental results demonstrated that the proposed architecture achieves better performance compared to majority of its state-of-the-art competitors in almost all problem instances.

Issue Mechanism for Embedded Simultaneous Multithreading Processor

Simultaneous Multithreading (SMT) technology enhances instruction throughput by issuing multiple instructions from multiple threads within one clock cycle. For in-order pipeline to each thread, SMT processors can provide large number of issued instructions close to or surpass than using out-of-order pipeline. In this work, we show an efficient issue logic for predicated instruction sequence with the parallel flag in each instruction, where the predicate register based issue control is adopted and the continuous instructions with the parallel flag of '0' are executed in parallel. The flag is pre-defined by a compiler. Instructions from different threads are issued based on the round-robin order. We also introduce an Instruction Queue skip mechanism for thread if the queue is empty. Using this kind of issue logic, we designed a 6 threads, 7-stage, in-order pipeline processor. Based on this processor, we compare round-robin issue policy (RR(T1-Tn)) with other policies: thread one always has the highest priority (PR(T1)) and thread one or thread n has the highest priority in turn (PR(T1-Tn)). The results show that RR(T1-Tn) policy outperforms others and PR(T1-Tn) is almost the same to RR(T1-Tn) from the point of view of the issued instructions per cycle.

デスクトップグリッド環境におけるタスクスケジューリングアルゴリズムＲＲ理論の実証と進化戦略の同期待ち時間削減について

This paper empirically investigates the effect of Desktop Grid Environment on the computational cost of Evolution Strategies (ES). Especially, for task scheduling, List Scheduling with Round-robin order Replication (RR) is adopted to reduce waiting time due to synchronization in ES. Computer simulations are conducted which compare with the loss energy of theoretical maximum value and an actual maximum measurement on Desktop Grid Environment for ES. Results on RR prove that the loss energy of an actual maximum measurement is less than that of theoretical maximum value. Moreover, RR can reduce the synchronous waiting time and improve parallel efficiency in comparison with Work Queue algorithm.

Integrating Temporal Distribution Information into Event-Based Summarization

In this paper, we present event-based summarization and investigate whether it can be enhanced by integrating temporal distribution information. We refer to events as event terms and the associated event elements. Event terms represent actions themselves and event elements are commonly those verb arguments. After anchoring events on the time line, we explore two statistical measures, i.e. tf*idf and x2, for evaluating the importance of events on each day. Summary sentences are selected based on the weights of the events contained in them, in either sequential or round robin order. Experiments show that the combination of time-based tf*idf weighting scheme and sequential sentence selection strategy can improve the quality of summaries significantly. The improvement can be attributed to its capability of representing the trend of news topics based on event temporal distributions.

A CSMA/CD compatible MAC for real-time transmissions based on varying collision intervals

This paper suggests a CSMA/CD compatible MAC protocol for real-time transmissions in a shared Home or Small Office Local Area Network. The new MAC is based on the distributed assignment of special TAG numbers to the stations transmitting real-time traffic. These TAG numbers determine a Round Robin order of transmissions among the real-time stations. They also help in resolving collisions among real time stations by setting the length of the Jam signal, transmitted in case of a collision, to be a function of the TAG number. In a collision the station with the highest TAG number, and so with the longest Jam, is persisting with its Jam transmission for the longest until all the other stations defer. Thus, the collision terminates and the longest persisting station can transmit its packet successfully. The new protocol enables stations implementing the IEEE 802.3 MAC standard to transmit on the same network with stations implementing the new protocol. After introducing the protocol, we compute an upper bound on the access delay that the protocol guarantees and prove the correctness of the distributed TAG assignment procedure. Finally, we simulate the protocol in a network consisting stations implementing the new protocol together with stations implementing the standard IEEE 802.3 MAC. We show that the access delays of the stations transmitting real-time traffic are indeed bounded as predicted.

Round-robin scheduling for max-min fairness in data networks

The author studies a simple strategy, proposed independently by E.L. Hahne and R.G. Gallager (1986) and M.G.H. Katevenis (1987), for fairly allocating link capacity in a point-to-point packet network with virtual circuit routing. Each link offers its packet transmission slots to its user sessions by polling them in round-robin order. In addition, window flow control is used to prevent excessive packet queues at the network nodes. As the window size increases, the session throughput rates are shown to approach limits that are perfectly fair in the max-min sense. If each session has periodic input (perhaps with jitter) or has such heavy demand that packets are always waiting to enter the network, then a finite window size suffices to produce perfectly fair throughput rates. The results suggest that the transmission capacity not used by the small window session will be approximately fairly divided among the large window sessions. The focus is on the worst-case performance of round-robin scheduling with windows. >

The Linear Software Reliability Model and Uniform Testing

The Jelinski-Moranda, Shooman, and Musa software reliability models all predict that the software error detection rate in a software system is a linear function of the detected errors. The basic differences among the models are that the error rates are, respectively, in terms of calendar-time, manpower, and computer-time. The models are simple to use for estimating the number of errors still in the tested software. Published studies generally show that error rates during system testing correlate best with the Musa model, and progressively less with the Shooman, and Jelinski-Moranda models. Simulation shows that, with respect to the number of detected errors, 1) testing the functions of a software system in a random or round-robin order gives linearly decaying system-error rates, 2) testing each function exhaustively one at a time gives flat system-error rates, 3) testing different functions at widely different frequencies gives exponentially decaying system-error rates, and 4) testing strategies which result in linear decaying error rates tend to requlire the fewest tests to detect a given number of errors.