Robust SRAM Cell Research Articles

Circuit-level technique to design robust SRAM cell against radiation strike

Circuit-level technique to design robust SRAM cell against radiation strike

Evaluation of static noise margin of 6T SRAM cell using SiGe/SiC asymmetric dual‐kspacer FinFETs

This work aims to investigate the device performance of silicon–germanium (SiGe)/Si carbide (SiC) source/drain (S/D) asymmetric dual-k spacer underlap Fin-field-effect transistor (SiGe/SiC-AsymD-k FinFET) with Si channel for high performance and robust SRAM cell. Strain-induced mobility enhancement due to the Si1−x Ge x /Si1−y C y S/D leads to a significant drive current enhancement of the proposed device. The introduced asymmetric dual-k spacer at source side offers excellent gate control over the channel. By exploiting asymmetry in current, the authors prove that it is possible to achieve mitigation of read–write conflict in 6T SRAM bit cell. SiGe/SiC-AsymD-k FinFET SRAM offers 8.39% improvement in hold static noise margin, 14.28% in read and 18.06% in write mode over conventional FinFET-based 6T SRAM bit cell. When compared to conventional FinFET 6T SRAM bit cell, the proposed 6T SRAM bit cell shows lesser temperature sensitivity of cell stability.

Pseudo differential multi-cell upset immune robust SRAM cell for ultra-low power applications

This paper presents a pseudo differential 12 transistor (PD12T) ultra-low leakage, fully half-select-free robust SRAM cell with good static and dynamic read/write performance. The proposed cell offers best Read/Hold SNM, Write Margin (WM) and least leakage power among all the cells considered in this work while causing an area overhead of 2.5× of that of 6T cell. Simulation results at VDD = 0.5 V show that PD12T cell offers 4.24× higher RSNM, 1.62× higher WM, 1.9× smaller leakage power (at 50 °C) as compared to 6T SRAM. The proposed cell offers VDD,min = 140 mV which is 260 mV smaller than that for 6T cell. When operated at VDD,min, the proposed cell consumes 13.6× smaller mean leakage power. The Ion/Ioff ratio of the proposed cell is more than 10× as compared to 6T cell and it holds potential to compensate for the area overhead by having more number of cells connected to the same bitline. The proposed cell is also suitable for all-TFET implementation as it requires only unidirectional current flow through transistors. Monte Carlo simulations using HSPICE with 16 nm PTM were performed by incorporating local and global variations and it is observed that the proposed cell offers high robustness against PVT variations. The proposed cell has highest critical charge among all other considered cells, which means that it is least vulnerable to soft-errors. The proposed PD12T also offers the best Electrical Quality Metric (EQM) among the cells considered in this work. The MC simulations for HSNM of row and column half-selected cells show that the mean value of SNM is approximately 30% of VDD. Therefore, the proposed cell can be used for bit-interleaving architecture to achieve multi-cell upset immunity and could be a good choice for applications that demands high stability, moderate speed and ultra-low power.

Single event multiple upset-tolerant SRAM cell designs for nano-scale CMOS technology

In this article, two soft error tolerant SRAM cells, the so-called RATF1 and RATF2, are proposed and evaluated. The proposed radiation hardened SRAM cells are capable of fully tolerating single event upsets (SEUs). Moreover, they show a high degree of robustness against single event multiple upsets (SEMUs). Over the previous SRAM cells, RATF1 and RATF2 offer lower area and power overhead. The Hspice simulation results through comparison with some prominent and state-of-the-art soft error tolerant SRAM cells show that our proposed robust SRAM cells have smaller area overhead (RAFT1 offers 58% smaller area than DICE), lower power delay product (RATF1 offers 231.33% and RATF2 offers 74.75% lower PDP compared with DICE), much more soft error robustness, and larger noise margins.

A Robust 10T SRAM Cell with Enhanced Read Operation

This paper presents a new 10T SRAM cell that has enhanced read speed along with good read and write stability. While the read access time of the proposed cell is 0.72x and 0.83x smaller as compared to the two most popular 10T SRAM cells at 50C; the read SNM is 1.16x and 1.05x higher compared to existing 10T cells. Though the read-write power of the proposed cell is higher with respect to the existing 10T cells; nevertheless, it consumes lower power as compared to the conventional 6T cell. Layout using 45nm technology rule shows that the proposed cell consumes 15% smaller area as compared to popular Schmitt-trigger based 10T SRAM cell. Also, the results of Monte-Carlo simulation show that the proposed cell is more robust against process variations. Therefore, the proposed 10T SRAM cell can be used where the speed and robustness are the primary requirements. General Terms High speed SRAM cell, Robust SRAM cell, Differential Read-Write SRAM cell.

A 32 kb Macro with 8T Soft Error Robust, SRAM Cell in 65-nm CMOS

A 32-kb macro containing an eight-transistor soft error robust SRAM cell with differential read and write capabilities is presented. The 8T cell does not have dedicated access transistors, and its quad-latch configuration stores data on four interlocked storage nodes. The macro was designed in a 65-nm CMOS process. The cell demonstrates excellent read data stability down to 0.55 V and is well suited for low-voltage, low-power applications. Neutron radiation testing on the macro exhibits at least $ 15\times $ improvement in Failure in Time (FIT) rate compared with the conventional 6T SRAM cell in 65-nm CMOS technology.

A Soft Error Tolerant 10T SRAM Bit-Cell With Differential Read Capability

We propose a quad-node ten transistor (10 T) soft error robust SRAM cell that offers differential read operation for robust sensing. The cell exhibits larger noise margin in sub-0.45 V regime and 26% less leakage current than the traditional soft error tolerant 12 T DICE SRAM cell. When compared to a conventional 6 T SRAM cell, the proposed cell offers similar noise margin as the 6 T cell at half the supply voltage, thus significantly saving the leakage power. In addition, the cell exhibits 98% lower soft error rate than the 6 T cell in accelerated neutron radiation tests carried out at TRIUMF on a 32-kb SRAM implemented in 90-nm CMOS technology.