Robust Fault Model Research Articles

Robust Fault Models Where Undetectable Faults Imply Logic Redundancy

We define a robust fault model as a model where the existence of an undetectable fault implies the existence of logic redundancy. The stuck-at fault model is robust, but other fault models such as certain bridging and interconnect open fault models are not. A robust fault model provides a mechanism to synthesize circuits in which all the target faults are detectable and 100% fault coverage is achievable. This is important since it provides a direct link between test quality and the circuit synthesis. We discuss robust fault models for bridging faults and interconnect open faults, and their use as part of a test generation process for a non-robust fault model.

Necessary and sufficient conditions for hazard-free robust transistor stuck-open-fault testability in multilevel networks

The authors address the problem of synthesizing circuits that are highly testable for transistor stuck-open fault testability in arbitrary, multilevel networks. They consider single stuck-open faults that are detectable using two-pattern tests, under a robust fault model wherein hazards, races, or glitches cannot invalidate a test. Using these results the authors show that algebraic factorization, including the constrained use of the complement, can be used to synthesize fully-stuck-open-fault testable multilevel networks. They provide a comprehensive set of practical results. >