Rms Period Jitter Research Articles

A 2.5 ppm/°C 1.05-MHz Relaxation Oscillator With Dynamic Frequency-Error Compensation and Fast Start-Up Time

This paper presents a 1.05 MHz, on-chip RC relaxation oscillator (ROSC) with a temperature coefficient (TC) of 2.5 ppm/°C and an absolute variation of 100 ppm over the body-compatible range of 0-40°C. The TC increases to 4.3 ppm/°C over the range from -15 °C to 55 °C. The high temperature stability is achieved using a PTAT current reference and a TC-tunable resistor bank for first-order frequency error compensation along with a digital frequency compensation (DFC) block using a single-bit temperature sensor for second-order compensation. A measured RMS period jitter of 160 ps is achieved with a high-speed comparator. The active power consumption of the ROSC is 69 μW with a 1-V supply, and the leakage power consumption is 110 nW, while power gated. The ROSC achieves a fast startup time of 8 μs by employing a voltage buffer to quickly stabilize the voltage reference.

Fast locking, startup-circuit free, low area, 32-phase analog DLL

This work presents 32-phase analog delay-locked-loop (DLL) having fast locking ability, startup-circuit free operation, and a low area with improved DNL-INL performance. The proposed faster delay-cell and the new bias-circuit enable startup-circuit free operation under process-voltage-temperature (PVT) variation, while the DLL achieves low area and faster locking by using a small filter capacitor. Again, input and output clocks pass through the respective CMOS buffer before the phase detector (PD) for load matching, which reduces DNL-INL in the DLL. The analog DLL locks in less than 54 or 56 clock cycles depending upon initial control voltage (supply or ground voltage) with 100 MHz input clock. The DLL generates 32-phase clocks with a bin-size of 312.5 ps, the peak-to-peak period jitter of 9.51 ps, the rms period jitter of 1.36 ps, the phase-offset error of 4.72 ps, DNL and INL less than ±0.11 LSB. The design consumes 3.54 mW power with a supply voltage of 3.3 V, and an area of 0.017 mm2 in UMC 180 nm MMRF technology. © 2001 Elsevier Science. All rights reserved

A High-Resolution 2-GHz Fractional-N PLL With Crystal Oscillator PVT-Insensitive Feedback Control

This letter presents a 2-GHz fractional-N phase-locked loop (PLL) with a high-precision delta–sigma digital-to-analog converter (DAC) to overcome the frequency deviation of a crystal oscillator due to manufacturing process, supply voltage, and temperature (PVT). The delta–sigma DAC with high power efficiency and linearity consists of a second-order delta–sigma modulator, a finite impulse response filter, and a low-pass filter. With the proposed PLL architecture, the frequency resolution can be lower than a few thousands of pulse per minute. The PLL is implemented in a 0.13- $\mu \text{m}$ 1P6M CMOS process. With temperature from −40 °C to 80 °C, the measured results of 15 chips show that the frequency deviation of output frequency in PVT decreases from 1 to 0.002 ppm. The phase noise of PLLs is less than −126 dBc/Hz at 1-MHz offset at a carrier frequency of 1.99 GHz. The rms period jitter is below 1 ps at 1.99 GHz, while consuming a total power of no more than 10 mW.

Near‐threshold all‐digital PLL with dynamic voltage scaling power management

A near-threshold all-digital phase-locked loop (ADPLL) with a power management unit (PMU) is presented to make the proposed ADPLL work reliably across variations and power consumption as well is reduced. When operated under near-threshold condition from 0.52 to 0.58 V VDD, the gated digitally controlled oscillator frequency range is from 90.8 to 245.7 MHz. When the ADPLL is operated at 0.52 V VDD, a lock-in time of 9.5 μs at 100 MHz output clock frequency is measured with an rms period jitter of 0.17% UI. With the PMU, the ADPLL power reduction at 130 MHz output frequency is 39% and the buck converter power consumption is nearly 30 μW. Consequently, the proposed ADPLL with PMU is suitable to event-driven or low-voltage applications.

Fully Integrated Frequency Reference With 1.7 ppm Temperature Accuracy Within 0–80°C

A fully integrated 52 MHz frequency reference, designed in a 0.35 μm CMOS process, achieves 1.7 ppm frequency temperature accuracy within 0 to 80°C using a nonlinear compensation technique. The proposed low TC <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</sub> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> reference oscillator achieves the lowest reported uncompensated temperature coefficient, i.e., 65.25 ppm/°C, among the integrated frequency references. The output reference frequency is obtained by dividing the differential LC Colpitts oscillator output operating at 1.6 GHz. Oscillator core dissipates 14 mW from 2.5 V. The blocks related to the temperature compensation scheme and the remaining system blocks consume 3 mW and 165 mW from 3.3 V supply, respectively. The measured phase noise of 52 MHz output is -94 dBc/Hz at 10 kHz offset frequency and rms period jitter is 3.2 ps.

A 0.8–2 GHz Fully-Integrated QPLL-Timed Direct-RF-Sampling Bandpass $\Sigma \Delta$ ADC in 0.13 $\mu$m CMOS

A reconfigurable bandpass continuous-time ΣΔ RF ADC tunable over the 0.8-2 GHz frequency range is presented. System- and circuit-level innovations provide low power consumption and reduced circuit complexity. The proposed architecture operates in both the first- and second-Nyquist zones to enable a wide tuning range from a fixed sampling frequency of 3.2 GHz. A fully-integrated on-chip quadrature phase-locked loop (QPLL) allows quadrature phase synchronization between a raised-cosine DAC and a quantizer. Implemented in 0.13 μm CMOS the fully-integrated prototype achieves SNDR values of 50 dB, 46 dB, and 40 dB over a 1 MHz bandwidth at 796.5 MHz, 1.001 GHz and 1.924 GHz carrier frequencies, respectively, with a total power consumption of 41 mW. The measured phase noise of the QPLL is -113 dBc/Hz at an offset frequency of 1 MHz and the reference spur is - 74.5 dBc. The RMS period jitter is 1.38 ps at 3.2 GHz.