Current-mode signalling significantly increases the bandwidth of on-chip interconnects and reduces the overall propagation delay. The inductive effect of interconnects is more dominant in submicron technologies. This is because an RC interconnects model results in a significant error in delay estimation. Consequently to avoid such errors, a delay model for current-mode signalling is proposed for RLC interconnect line in the present work. RLC interconnect line is modelled using characteristic impedance of line. The inductive effects which are dominant at lower technology nodes are modelled as an equivalent resistance (). RLC line is modelled into a new equivalent ReffC interconnect line. The efficacy of the proposed model is validated for 8 and 10 mm interconnect lines. It is inferred that current mode provides better performance compared to the voltage-mode signalling. It is found that current-mode signal transporting technique provides higher speed improvements. Secondly, the damping factor of a lumped RLC circuit is shown to be a useful figure of merit. The analysis is carried out for 180 nm technology node.