Ring Oscillator Speed Research Articles

Design of High Speed and Low-Power Ring Oscillator Circuit in Recessed Source/Drain SOI Technology

In this paper, switching speed of CMOS inverter and Ring Oscillator is analyzed for the first time using Triple-Metal-Gate (TMG) Recessed-Source/Drain (Re-S/D) SOI MOSFET. Re-S/D SOI MOSFET has the capability to reduce the series resistance of the device due to the extended depth of source and drain into buried oxide layer. So the current drive capability of this device is improved which in turn improves the input/output switching in the inverter and ring oscillator. In this paper, transfer characteristics, delay and frequency is analyzed for inverter as well as for ring oscillator with TMG Re-S/D SOI MOSFET. DC and transient analysis such as transfer characteristics, noise margin, power dissipation, delay, and frequency is done for CMOS inverter and ring oscillator. Also, the Voltage Transfer Characteristic (VTC) has been compared with the available SMG and DMG structures of Re-S/D FD SOI MOSFET for the analysis switching behavior. This DC and transient simulation are performed using 2-dimensional numerical TCAD simulator ATLAS from Silvaco.

Benchmarking of MoS2FETs With Multigate Si-FET Options for 5 nm and Beyond

In this paper, we benchmark the performance of monolayer and bilayer MoS2 FETs (MFETs) against various multigate (MuG) Si-FET options, such as FinFETs and lateral and vertical nanowire FETs, for a 5-nm node and beyond. We compare the performance metrics of all the device options at the ring-oscillator (RO) level, accounting for not only intrinsic and extrinsic parasitic elements but also interconnects. Using the atomistic two-band ballistic quantum transport simulations, we evaluate ON-current and intrinsic capacitances for MoS2-based devices. Furthermore, we calibrate two-band model currents with more sophisticated full-band diffusive simulations to obtain realistic performance metrics at the circuit level. We show that both the intrinsic and parasitic capacitances of a single-gate MFET are lesser than those of a double-gate (DG) MFET, resulting in 13% lesser energy consumption. A DG bilayer (DGBL) MFET shows the best performance among different MFETs. In comparison toMuG FETs, the DGBL MFET offers not only lower energy consumption but also 35%–45% lower speed. In the end, to meet the target performance, we evaluate the impact of the device current, contact resistance, and back-end-of-the-line load on the speed of RO with the DGBL MFET.

Insulating Halos to Boost Planar NMOSFET Performance

Short-channel controllability by insulating halo (IH) is investigated using the NFET strained-Si technology. By embedding SiO2/Si3N4 insulators in the halo regions, the increase of halo implant concentration reduces source/drain depths and improves short-channel effects such as drain-induced barrier lowering. With Ioff similar to the control device at the same gate length by adjusting the threshold voltage, the channel doping can be reduced, and the channel mobility increases due to the decrease of vertical electric field. Moreover, IHs reduce the shallow trench isolation compressive stress in the channel and yield a high-electron mobility enhancement. The device performance is optimized based on the simulation design. Up to a 23% Ion improvement was experimentally achieved by optimal IH insertion. A 7% lower junction capacitance and an 8% ring oscillator speed improvement are demonstrated when the IH is adopted in the NFET alone. Moreover, device reliability is carefully examined and is not adversely impacted by IH insertion.

65 nm LP/GP mix low cost platform for multi-media wireless and consumer applications

A complete 65 nm CMOS platform, called LP/GP Mix, has been developed employing thick oxide transistor (IO), Low Power (LP) and General Purpose (GP) devices on the same chip. Dedicated to wireless multi-media and consumer applications, this new triple gate oxide platform is low cost (+1mask only) and saves over 35% of dynamic power with the use of the low operating voltage GP. The LP/GP mix shows competitive digital performance with a ring oscillator (FO = 1) speed equal to 7 ps per stage (GP) and 6T-SRAM static power lower than 10 pA/cell (LP). Compatible with mixed-signal design requirements, transistors show high voltage gain, low mismatch factor and low flicker noise. Moreover, to address mobile phone demands, excellent RF performance has been achieved with F T = 160 GHz for LP and 280 GHz for GP nMOS transistors.

Systematic Characterization of Pseudomorphic (110) Intrinsic SiGe Epitaxial Films for Hybrid Orientation Technology with Embedded SiGe Source/Drain

AbstractPFET devices fabricated using embedded SiGe source/drain on (110) silicon substrates have shown significant performance improvement compared to PFETs with embedded SiGe on (100) SOI substrates. In this paper, we report a systematic material characterization on the epitaxial SiGe films, both on blanket and patterned substrates, and corresponding PFET performance data. The SiGe films were deposited in an RTCVD system. The epitaxial growth rate on (110) substrates was 30% lower than on (100), and 30% higher on patterned device wafers compared to blanket wafers. Films were characterized using an array of methods such as High Resolution XRD (for Ge composition, strain and thickness), Auger (for Ge composition), UV Raman microprobe (for strain), AFM (for surface morphology), and TEM (for epi quality). The Ge compositions determined by XRD and Auger are in excellent agreement (15~16%). The amount of strain extracted from the Raman measurements is also consistent with the amount determined by XRD, which is 0.60%, corresponding to a fully strained Si0.85Ge0.15 film. AFM showed much higher RMS and Rmax for the SiGe films on (110) substrates compared to those on (100) substrates. XTEM showed high crystalline quality with very low defect count in the SiGe source/drain and Si channel regions. PFETs with an embedded Si0.85Ge0.15 source/drain on hybrid orientation (HOT) substrates provided a 30% advantage in drive current and a 23% enhancement in ring oscillator speed compared to control devices on (100) SOI wafer.

Investigation of the source/drain asymmetric effects due to gate misalignment in planar double-gate MOSFETs

A planar double-gate SOI MOSFET (DG-SOI) with thin channel and thick source/drain (S/D) was successfully fabricated. Using both experimental data and simulation results, the S/D asymmetric effect induced by gate misalignment was studied. For a misaligned DG-SOI, there is gate nonoverlapped region on one side and extra gate overlapped region on the other side. The nonoverlapped region introduces extra series resistance and weakly controlled channel, while the extra overlapped region introduces additional overlap capacitance and gate leakage current. We compared two cases: bottom gate shift to source side (DG/spl I.bar/S) and bottom gate shift to drain side (DG/spl I.bar/D). At the same gate misalignment value, DG/spl I.bar/S resulted in a larger drain-induced barrier lowering effect and smaller overlap capacitance at drain side than DG/spl I.bar/D. Because of reduced drain-side capacitance, the speed of three-stage ring oscillator of DG/spl I.bar/S, with 20% gate misalignment length (L/sub mis/) over gate length (L/sub g/), or L/sub mis//L/sub g/=20%, was faster than that of two-gate aligned DG-SOI.

A 15 nm Ultra-thin Body SOI CMOS Device with Double Raised Source/Drain for 90 nm Analog Applications

Fully-depleted silicon-on-insulator (FD-SOI) devices with a 15 nm SOI layer thickness and 60 nm gate lengths for analog applications have been investigated. The Si selective epitaxial growth (SEG) process was well optimized. Both the single-raised (SR) and double-raised (DR) source/drain (S/D) processes have been studied to reduce parasitic series resistance and improve device performance. For the DR S/D process, the saturation currents of both NMOS and PMOS are improved by 8 and 18%, respectively, compared with the SR S/D process. The self-heating effect is evaluated for both body contact and body floating SOI devices. The body contact transistor shows a reduced self-heating ratio, compared with the body floating transistor. The static noise margin of an SOI device with a 1.1 μm 2 6T-SRAM cell is 190 mV, and the ring oscillator speed is improved by 25 % compared with bulk devices. The DR S/D process shows a higher open loop voltage gain than the SR S/D process. A 15 nm ultra-thin body (UTB) SOI device with a DR S/D process shows the same level of noise characteristics at both the body contact and body floating transistors. Also, we observed that noise characteristics of a 15 nm UTB SOI device are comparable to those of bulk Si devices.

Sub-50 nm gate length SOI transistor development for high performance microprocessors

Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40 nm gate length (L GATE) PD SOI transistors into volume manufacturing for high-speed microprocessors. The key innovations developed for this transistor in order to overcome classical gate oxide and L GATE scaling is an unique differential triple spacer structure, stressed overlayer films inducing strain in the Silicon channel and optimized junctions. This transistor structure yields an outstanding ring oscillator speed with an unloaded inverter delay of 5.5 ps. The found improvements are highly manufacturable and scaleable for future device technologies like FD SOI.

Fully Depleted SOI Complementary MOS Device with Raised Source/Drain for 90 nm Embedded Static RAM Technology

Fully depleted silicon-on-insulator (FD SOI) devices with 70 nm gate lengths for embedded static random access memory (SRAM) technology were investigated for different SOI film thickness. Transistor performances of 700 µA/µm and 320 µA/µm were obtained for n-type and p-type metal-oxide semiconductor field effect transistor (NMOSFET and PMOSFET) devices, respectively at 1.0 V operation voltage and Ioff=75 nA/µm. Si selective epitaxial growth (SEG) process was well optimized. Both the single raised (SR) and double raised (DR) source/drain process were studied to reduce parasitic series resistance. For the DR process, both NMOSFET and PMOSFET performance are improved by 9 and 13% respectively, compared to the SR process. Drain induced barrier lowering (DIBL) was improved from 100 mV to 13 mV as the SOI film thickness was scaled down from 50 nm to 17 nm. Due to the self-heating effect, the AC current is 15% higher than the DC current for the case of 40 nm SOI thickness. The static noise margin (SNM) for a 1.1 µm2 6T-SRAM cell was 210 mV and ring oscillator speed was improved by 24% compared to bulk devices.

A methodology for deep sub-0.25 μm CMOS technology prediction

We present a novel methodology for characterization of sub-quartermicron CMOS technologies. It involves process calibration, device calibration employing two-dimensional device simulation and automated Technology Computer Aided Design (TCAD) optimization and, finally, transient mixed-mode device/circuit simulation. The proposed methodology was tested on 0.25 /spl mu/m technology and applied to 0.13 /spl mu/m technology in order to estimate ring oscillator speed. The simulation results show an excellent agreement with available experimental data.

Experimental studies on deep submicron CMOS scaling

N- and surface channel p-MOSFETs and CMOS ring oscillators with channel lengths down to and physical gate oxide thicknesses of 2.5 nm-5.8 nm were fabricated. The parasitic SD series resistance, threshold voltages, finite thickness of inversion layer including quantum and polysilicon gate depletion effects, drain saturation current, load capacitance of ring oscillator and ring oscillator speed were characterized at voltages from 1.5 to 3.3 V. The results confirmed the accuracy of the analytical models recently developed. The existence of an optimum gate oxide for given , , and is demonstrated from both the analytical model and the experimental data.

An extraction method to determine interconnect parasitic parameters

Interconnect parasitic parameters in integrated circuits have significant impact on circuit speed. An accurate monitoring of these parameters can help to improve interconnect performance during process development, provide information for circuit design, or give useful reference for circuit failure analysis. Existing extraction methods either are destructive (such as SEM measurement) or can determine only partial parasitic parameters (such as large capacitor measurement). In this paper, we present a new method for extracting interconnect parasitic parameters, which can simultaneously determine the interlayer and intralayer capacitances, line resistance, and effective line width. The method is based on two test patterns of the same structure with different dimensions. The structure consumes less wafer area than existing methods. The method shows good agreement with SEM measurement of dielectric thickness in both nonglobal planarized and chemical-mechanical polished processes, and gives accurate prediction of the process spread of a ring oscillator speed over a wafer.

Performance and reliability aspects of FOND: a new deep submicron CMOS device concept

The electrical performance and the hot-carrier degradation behavior of a new type of fully overlapped device called FOND (Fully Overlapped Nitride-etch defined Device) is analyzed and compared to that of conventional LDD devices. Similar current driveability is found for the FOND devices compared to conventional LDD devices although in the FOND device significantly smaller concentrations are used for the lightly doped n/sup -/-regions. For the overlapped device, a higher gate and overlap capacitance is found, originating from a larger poly length and self-alignment of the junction implant to the poly. For identical voltage conditions, this is reflected in a somewhat lower ring oscillator speed, compared to the LDD case. Concerning reliability, it is shown that deep submicron FOND devices can easily exceed the lifetime of the conventional LDD devices by two orders of magnitude. Based on experimental and simulation results, this higher hot-carrier resistance is explained by a smaller hot-carrier generation and a lower sensitivity of the overlapped device to hot-carrier damage. For the nMOS transistors, the lower generation of damage is the result of the lower lateral electric field due to the low n/sup -/ concentration and the overlap of the polysilicon gate on the n/sup -/ region while the suppressed sensitivity is due to the complete overlap. Compared to LDD devices, the use of fully overlapped devices creates a wider process and reliability margin that can be used to optimize other electrical parameters.

The effects of source/drain resistance on deep submicrometer device performance

As MOSFET channel lengths approach the deep-submicrometer regime, performance degradation due to parasitic source/drain resistance (R/sub sd/) becomes an important factor to consider in device scaling. The effects of R/sub sd/ on the device performance of deep-submicrometer non-LDD (lightly doped drain) n-channel MOSFETs are examined. Reduction in the measured saturation drain current (R/sub sd/=600 Omega - mu m) relative to the ideal saturation current (R/sub sd/=0.0 Omega - mu m) is about 4% for L/sub eff/=0.7 mu m and T/sub ox/=15.6 nm and 10% for L/sub eff/=0.3 mu m and T/sub ox/=8.6 nm. Reduction of current in the linear regime and reduction of the simulated ring oscillator speed are both about three times higher. The effect of salicide technologies on device performance is discussed. Projections are made of the ultimate achievable performance.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Relating CMOS inverter lifetime to DC hot-carrier lifetime of NMOSFETs

The authors report that comparison with measured 75-MHz CMOS ring-oscillator speed degradation suggests that quasi-static circuit aging simulations using DC stress data do not underestimate circuit degradation. Roughly speaking, 10% degradation in NMOSFET linear current results in only about 1.3% increase in CMOS inverter propagation delay. This 10% current degradation occurs in an inverter-based circuit over a time that is about six times the MOSFET DC lifetime at maximum I/sub sub/ and about 30 times the DC lifetime at maximum I/sub sub//sup 3//I/sub ds//sup 2/. >