Operation Of Ring Oscillators Research Articles

Simulation of a ring oscillator operation during γ-ray irradiation using the TID response model of MOSFETs and its experimental verification

The response of N-type MOSFET characteristics to TID (Total Ionizing Dose) effects caused by γ-ray irradiation was modeled as a sum of two exponential functions which expresses the charge accumulation of the oxide traps and the interface traps respectively. This model was applied to the circuit simulation of a ring oscillator operation. It was shown that the simulation result reproduces the variation in the measured oscillation frequency experimentally. The simulation also showed that there is an optimum size ratio between N-type MOSFET and P-type MOSFET which can minimize the variation in oscillation frequency due to TID effects. These obtained results verified that the proposed method can be applied to the prediction of response in a dynamic operation circuit to TID effects.

Fabrication of ring oscillators using organic molecules of phenacene and perylenedicarboximide.

Organic field-effect transistors (FETs) can be applied to radio-frequency identification tags (RFIDs) and active-matrix flat-panel displays. For RFID application, a cardinal functional block is a ring oscillator using an odd number of inverters to convert DC voltage to AC. Herein, we report the properties of two ring oscillators, one formed with [6]phenacene for a p-channel FET and N,N′-dioctyl-3,4,9,10-perylenedicarboximide (PTCDI-C8) for an n-channel FET, and one formed with 3,10-ditetradecylpicene ((C14H29)2-picene) for a p-channel FET and PTCDI-C8 for an n-channel FET. The former ring oscillator provided a maximum oscillation frequency, fosc of 26 Hz, and the latter a maximum fosc of 21 Hz. The drain–drain voltage, VDD, applied to these ring oscillators was 100 V. This may be the first step towards a future practical ring oscillator using phenacene molecules. The values of field-effect mobility, μ in the p-channel [6]phenacene FET and n-channel PTCDI-C8 FET, which form the building blocks in the ring oscillator with an fosc value of 26 Hz, are 1.19 and 1.50 × 10−1 cm2 V−1 s−1, respectively, while the values in the p-channel (C14H29)2-picene FET and n-channel PTCDI-C8 FET, which form the ring oscillator with an fosc of 21 Hz, are 1.85 and 1.54 × 10−1 cm2 V−1 s−1, respectively. The μ values in the p-channel FETs are higher by one order of magnitude than those of the n-channel FET, which must be addressed to increase the value of fosc. Finally, we fabricated a ring oscillator with ZrO2 instead of parylene for the gate dielectric, which provided the low-voltage operation of the ring oscillator, in which [6]phenacene and PTCDI-C8 thin-film FETs were employed. The value of fosc obtained in the ring oscillator was 24 Hz. In this ring oscillator, the VDD value applied was limited to 20 V. The durability of the ring oscillators was also investigated, and the bias stress effect on the fosc and the amplitude of the output voltage, Vout are discussed. This successful operation of ring oscillators represents an important step towards the realization of future practical integrated logic gate circuits using phenacene molecules.

Optimization of Stacked Nanoplate FET for 3-nm Node

In this article, various characteristics of nanoplate FET were studied based on TCAD simulation for a 3-nm node. The optimum geometry specification was proposed through comparison of RC delay from previous studies. Additionally, the impacts of self-heating effects (SHEs) in the 3-nm node were evaluated in the targeting device because it is expected that highly scaled areas such as channels have a negative effect on the performance due to low heat dissipation. This degradation was verified in a single device and in ring oscillator (RO) operation. pMOS is comparatively stronger than nMOS in terms of SHEs due to wider channel width. In RO operation, the influence of SHEs begins to appear at over 0.65 V through power and speed comparison. Therefore, an operation voltage under 0.65 V can be the optimal voltage to suppress SHEs.

Low‐Voltage Operation of Ring Oscillators Based on Room‐Temperature‐Deposited Amorphous Zinc‐Tin‐Oxide Channel MESFETs

AbstractSchottky diode FET logic (SDFL) ring oscillator circuits comprising metal‐semiconductor field‐effect transistors (MESFETs) based on amorphous zinc‐tin‐oxide (ZTO)n‐channels are presented. The ZTO channel layers are deposited entirely at room temperature by long‐throw magnetron sputtering. Best MESFETs exhibit on/off current ratios as high as 8.6 orders of magnitude, a sub‐threshold swing as low as 250 mV dec−1, and a maximum transconductance of 205 µS. Corresponding inverters show peakge gain magnitude (pgm) values of 83 with uncertainty levels as low as 0.5 V at an operating voltage of 5 V. Single stage delay times down to 277 ns are measured for three‐stage ring oscillators, corresponding to oscillation frequencies as high as 451 kHz. Oscillations are observed at operating voltages as low as 3 V. These results prove the feasibility of room‐temperature‐deposited, amorphous semiconducting oxide based integrated circuits with SDFL layout. The presented approach provides more efficient as well as fail‐safe device fabrication and similar oscillation frequencies at significantly lower operating voltages compared to conventional, high‐temperature processed logic circuits based on insulating gates.

Static and Dynamic Response Comparison of Printed, Single- and Dual-Gate 3-D Complementary Organic TFT Inverters

A dual-gate configuration has been introduced to organic thin-film transistors (TFTs) for full-depletion behavior to enhance the transconductance, subthreshold slope, and drain current on–off ratio. In this letter, we show how those dual-gate effects influence the static and dynamic responses of three-dimensional (3-D) complementary organic logic gates in comparison to their single-gate counterpart. For the comparative study, 3-D inverters and ring oscillators were fabricated by printing directly on plastic foil in both single- and dual-gate configurations. In the static inverter operation, the fully depleted characteristics of the dual-gate TFTs lead to an increase in voltage gain and a dramatic decrease in standby power consumption. In the dynamic ring oscillator operation, the two configurations have comparable gate delays because the use of an additional gate increases not only the drain current but also the load input gate capacitance. Our findings demonstrate the performance of an inverter that can represent the overall operation of complementary logic gates consisting of pull-up and pull-down networks, thereby providing significant insight into the printed organic TFT circuit design using dual gating effects.

Analysis of TID Process, Geometry, and Bias Condition Dependence in 14-nm FinFETs and Implications for RF and SRAM Performance

Total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high- $V_{\textit {th}}$ transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and $V_{\textit {th}}$ , while the low- $V_{\textit {th}}$ transistors exhibit a larger change in off-state leakage current. The “ worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state ( $V_{\textit {gs}}=V_{\textit {dd}}$ ). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low- $V_{\textit {th}}$ transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics.

Load adaptive start-up scheme for synchronous boost DC-DC converter

This paper presents a load adaptive soft-start scheme through which the inductor current of the synchronous boost DC-DC converter can trace the load current at the start-up stage. This scheme effectively eliminates the inrush-current and over-shoot voltage and improves the load capability of the converter. According to the output voltage, the start-up process is divided into three phases and at each phase the inductor current is limited to match the load. In the pre-charge phase, a step-increasing constant current gives a smooth rise of the output voltage which avoids inrush current and ensures the converter successfully starts up at different load situations. An additional ring oscillator operation phase enables the converter to start up as low as 1.4 V. When the converter enters into the system loop soft-start phase, an output voltage and inductor current detection methods make the transition of the phases smooth and the inductor current and output voltage rise steadily. Effective protection circuits such as short-circuit protection, current limit circuit and over-temperature protection circuit are designed to guarantee the safety and reliability of the chip during the start-up process. The proposed start-up circuit is implemented in a synchronous boost DC-DC converter based on TSMC 0.35 μm CMOS process with an input voltage range 1.4-4.2 V, and a steady output voltage 5 V, and the switching frequency is 1 MHz. Simulation results show that inrush current and overshoot voltage are suppressed with a load range from 0-2.1 A, and inductor current is as low as 259 mA when the output shorts to the ground.

Switching delay of a nonlatching Josephson gate evaluated from ring oscillator operation

The authors present the experimental results for the switching delay of a dc-biased nonlatching Josephson gate (a coupled-superconducting quantum interference device gate). The measurement is executed by the use of a ring oscillator (RO) method. A frequency-to-voltage converter is used to evaluate the oscillation frequency of the RO. The circuit is designed and fabricated using a 2.5-kA/cm/sup 2/ Nb/AlO/sub x//Nb Josephson junction technology. The results show the minimum switching delay of 18 ps.

A model-base comparison: GaAs/GaAlAs HBT versus silicon bipolar

A pure model-base comparison is made between the GaAs/ GaAlAs HBT and the silicon bipolar transistor for the high-speed switching performance under ring oscillator operation. Full utilization is made of our own modeling tools, which include a "physical" one-dimensional transistor model, a hybrid model to represent a realistic device structure, and a circuit simulator to allow direct access to the physical model. Delay time versus power characteristics, as well as dynamic carrier profiles are demonstrated, with discussion about limiting factors for the switching speed.

Direct-coupled logic operation of GaAs column gate FET

A ring oscillator operation is demonstrated employing normally-off 2 µm diameter column gate FET with 145 ps/gate delay time and with 64 fJ power-delay product. Delay time is discussed in terms of CR time constant comparison between MES and column structure. The column gate FET can realize much smaller "on" resistance comparing with MESFET.