RFID Tag IC Research Articles

VLSI Implementation of Area and Power Efficient Digital Control Circuit for HF RFID Tag Chip

A fully integrated area efficient digital control circuit based on the ISO/IEC 15693 protocol is proposed for high frequency RFID tag chip. The proposed circuit is mainly composed of pulse position modulation decoder, Manchester encoder, anticonllision, low power circuit and other control logic. It supports six different data rates, namely, low or high data rate with one subcarrier (6.62 or 26.48 Kbit/s), low or high data rate with two subcarriers (6.67 or 26.69 Kbit/s), fast data rate with one subcarrier (13.24 or 52.97 Kbit/s). The proposed digital control circuit was integrated in an RFID tag IC and was fabricated using a 0.18-µm 2P6M CMOS process with an area of 306µm by 326µm which is smaller than the existing designs. Besides of small area, the circuit has an advantage of low power with a power consumption of less than 50µW.

An Ultra Low-Power Solution for EEPROM in Passive UHF RFID Tag IC With a Novel Read Circuit and a Time-Divided Charge Pump

A dual power supply ultra low-power 1 kbits EEPROM for passive UHF RFID is presented. The read power source is 1 V, while the write power source is 1.65 V, which is only activated in the write mode. To reduce the power of the read circuit without impacting the performance, a pre-charge scheme, a feedback scheme and a self-detect circuit, combined with a special read time sequence are adopted. A time-divided charge pump is proposed to reduce the current surge of the charge pump at the startup phase. The EEPROM IP has been fabricated in a SMIC 0.18 μm 2P4M EEPROM process. The die size of the proposed EEPROM IP is 0.12 mm2. The read and write currents of the EEPROM IP are 1.18 μA and 33 μA respectively. Under a 110 temperature variation, the power variation of the read operation is 15%. The EEPROM IP is then verified in a full UHF RFID chip. Tested by a commercial reader at 4 W EIRP, the maximum read and write communication ranges are 6 m and 3 m respectively. The measured voltage drop of the output of rectifier Vrect caused by the current surge of the charge pump is smaller than 50 mV.

A 2-Kb One-Time Programmable Memory for UHF Passive RFID Tag IC in a Standard 0.18 $\mu$m CMOS Process

We present a 2-Kb one-time programmable (OTP) memory for UHF RFID applications. The OTP memory cell is based on a two-transistor (2-T) gate-oxide anti-fuse (AF) for low voltage operation. Reliability of memory cell is enhanced by limiting the maximum terminal voltages of thin-oxide and thick-oxide transistors to 1.8 V and 3.3 V, respectively. Improved low power circuit design techniques are used including auto shut-off for program mode and self-timed control for read mode. To further reduce power consumption, we develop a novel power-efficient charge pump. The designed OTP is successfully embedded into a UHF passive RFID tag IC that conforms to the EPCglobal Gen-2 standard. The tag chip was fabricated in a 0.18 m 1-poly 6-metal standard CMOS process with no additional masks. The total area of the chip including the I/Os and bonding pads is 2.3 × 1.5 mm2 where the OTP memory area is only 0.43 × 0.31 mm2. Our tag IC measurement shows that the read and write currents of the OTP memory are 17 μA and 58 μA, respectively.

New Analysis and Design of a RF Rectifier for RFID and Implantable Devices

New design and optimization of charge pump rectifiers using diode-connected MOS transistors is presented in this paper. An analysis of the output voltage and Power Conversion Efficiency (PCE) is given to guide and evaluate the new design. A novel diode-connected MOS transistor for UHF rectifiers is presented and optimized, and a high efficiency N-stage charge pump rectifier based on this new diode-connected MOS transistor is designed and fabricated in a SMIC 0.18-μm 2P3M CMOS embedded EEPROM process. The new diode achieves 315 mV turn-on voltage and 415 nA reverse saturation leakage current. Compared with the traditional rectifier, the one based on the proposed diode-connected MOS has higher PCE, higher output voltage and smaller ripple coefficient. When the RF input is a 900-MHz sinusoid signal with the power ranging from −15 dBm to −4 dBm, PCEs of the charge pump rectifier with only 3-stage are more than 30%, and the maximum output voltage is 5.5 V, and its ripple coefficients are less than 1%. Therefore, the rectifier is especially suitableto passive UHF RFID tag IC and implantable devices.

A CMOS voltage regulator for passive RFID tag ICs

SUMMARYA low‐power voltage regulator for passive RFID tag ICs is proposed in this paper. It consists of a self‐biased mutually compensated voltage reference, a low dropout (LDO) voltage regulation circuit and a power‐on‐reset (POR) circuit. It is fabricated in a commercial 0.18−µm CMOS technology and applied to a passive UHF RFID tag IC. The total quiescent current is 700 nA under a 1.8‐V supply. The output voltage of the regulator is 1.45 V with load capability of 50 µA. The temperature coefficients of the voltage reference and the output voltage are only 9 and 43 ppm/∘C, respectively. A POR signal with width pulse of 150 ns is generated for the digital part in the tag IC. Copyright © 2010 John Wiley & Sons, Ltd.

A circuit scheme to control current surge for RFID-NVM pumps

This paper presents a new circuit scheme to control the current surge in the boosting phase of an radio frequency idenfication–nonvolative memory pump. By introducing a circuit block consisting of a current reference and a current mirror, the new circuit scheme can keep the period-average current of the pump constantly below the desired level, for example, 2.5 μA. Therefore, it can prevent the rectified supply of the RFID tag IC from collapsing in the boosting phase of the pump. The presented scheme could effectively reduce the voltage drop on the rectified supply from more than 50% to even zero, but could cost less area. Moreover, an analytical expression to calculate the boosting time of a pump in the new scheme is developed.

New design of sense amplifier for EEPROM memory

We present a new sense amplifier circuit for EEPROM memory. The topology of the sense amplifier uses a voltage sensing method, having low cost and low power consumption as well as high reliability. The sense amplifier was implemented in an EEPROM realized with an SMIC 0.35-μm 2P3M CMOS embedded EEPROM process. Under the condition that the power supply is 3.3 V, simulation results showed that the charge time is 35 ns in the proposed sense amplifier, and that the maximum average current consumption during the read period is 40 μA. The novel topology allows the circuit to function with power supplies as low as 1.4 V. The sense amplifier has been implemented in 2-kb EEPROM memory for RFID tag IC applications, and has a silicon area of only 240 μm2.

Embeded EEPROM Memory Achieving Lower Power - New design of EEPROM memory for RFID tag IC

A 2-kb embedded EEPROM memory, operating over a wide voltage range (typically 2.5 V-5 V), was designed and fabricated using the SMIC 0.35-mum 2P3M CMOS embedded EEPROM process. The chip size is about 0.6 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The method of adding control transistors improved the static power dissipation. The transient power consumption of the charge pump circuit was greatly reduced by using a slowly varying clock. The proposed SA using a voltage sensing method also significantly improved the read power dissipation. By employing these techniques, a low-power embedded EEPROM memory with 40 muA read current and 250 muA page write current was developed, that achieved much lower power than EEPROM memory designs reported in scientific journals or conferences. This EEPROM memory was used in the ISO/IEC 15693-compatible RFID tag IC project

13.56 MHz RFID 태그 집적회로 설계

The RFID tag IC has been presently abstracting great attention in the world because it can be one of the important sensor elements in the ubiquitous sense network in the future. The 125 kHz and 13.56 MHz RFID tag IC`s have already been developed and now widely used in the world and the UHF band tag IC is under development. Domestically, the development of the 125 kHz tag IC was reported before, but there has been no report about the development of the 13.56 MHz tag IC up to now. In this paper, the results of the design, fabrication and measurement of a 13.56 MHz tag IC are discussed. The digital and the analog circuits for the chip were designed and the chip was fabricated using 0.35 ㎛ standard CMOS technology and measured with a separately prepared reader. It was found from the measurement results that it operated properly within 8 cm range of the reader.