RF Front-end Applications Research Articles

Testing and Analysis of MOSFET-Based Absorber Integrated Antenna for 5G/WiMAX/WLAN Applications.

A 3D electromagnetic circuit design and analysis of a MOSFET-based absorber active integrated antenna has been performed. It integrates a transmitting dual-band double material substrate (DMS) cylindrical surrounding patch antenna (CSPA) with a MOSFET-based absorber of reflected radio frequency power. It is a solution to the problem of performance degradation in the power amplifier (PA) resulting from antenna and PA impedance mismatch. This fully integrated MOSFET-based absorber antenna can absorb reflected RF power with a diode-based quasi-circulator as part of the integrated design circuitry. The antenna used for the proposed integrated design will operate at frequencies ranging from 2 GHz to 3 GHz and from 4.6 GHz to 6.1 GHz, thus providing a bandwidth of 1 GHz and 1.5 GHz at a resonance frequency of 2.5 GHz and 5.3 GHz, respectively. This makes it suitable for use in lower and upper bands of WLAN/WiMAX medium RF front-end applications. Furthermore, the condition for MOSFET connected to the absorber (IS ≤ ID and VDS = 0) has been satisfied at both instances of resonance. In this proposed design, an antenna radiation efficiency of 84% has been observed.

Compact low‐noise power amplifier design and implementation for millimetre wave frequencies

In this paper, we have designed and realized a two-stage low-noise power amplifier (LNPA) with resistive feedback network targeting for Ka-band compact RF front-end applications. Featuring the characteristics of both low noise and high power at the same time, the LNPA is expected to be a possible one-chip replacement of power and low noise amplifiers integrated in a conventional transceiver/receiver (T/R) module. Such configuration features size compactness while reduces implementation complexity which is of crucial importance for integration in antenna arrays with large number of antenna elements. Implemented in 0.15-μm GaAs pseudomorphic high electron mobility transistor (pHEMT) technology, the LNPA, operating at 36–40 GHz, exhibits a peak gain of 15.96 dB, a minimum noise figure of 2.88 dB, a power consumption of 152 mW and a measured 1-dB compression output power of 14.92 dBm at 38 GHz, respectively. The LNPA also featured a very good linearity performance with a measured output third-order interception point (IP3) of 22.22 dBm at 38 GHz.

A Multiband Directional Coupler Using SOI CMOS for RF Front-End Applications

This letter introduces a novel multiband directional coupler for RF front-end applications. Conventional narrowband directional couplers are widely used for mobile applications because of their compact size. However, excessive power loss due to strong coupling in the higher frequency range severely limits their bandwidth. To resolve this issue, we propose a dual directional coupler employing a coupling switching stage, where the asymmetric coupled lines can be electrically coupled or floated to mitigate severe coupling loss. The proposed coupler has been implemented to an integrated circuit using the silicon-on-insulator process. The measured results showed a considerably enhanced bandwidth from 0.69 to 4 GHz covering the entire frequency band of long-term evolution with a low power loss of less than −0.21 dB in the target frequency range.

Performance improvement of a reconfigurable series-shunt switch via asymmetric structure based RF-MEMS capacitive switch

This paper presents a series combination of metal to metal contact and capacitive RF-MEMS switches for multi-band wireless applications. For performance improvement a novel capacitive shunt switch is used and the response has been compared with a conventional shunt device. The proposed design shows the insertion loss better than 0.35 dB and return loss below 13.96 dB up to 30 GHz as compared to 1.64 dB insertion loss and 6.14 dB of return loss with conventional device. Isolation peaks of 75.33, 71.58 and 72.98 dB has been observed at 8.2, 7.3 and 15.5 GHz when left, right or both cantilevers are electro-statically actuated in the down-state respectively, whereas conventional device has peak only at 7.3 GHz. Further, a reduction of about 60 % in the pull-in voltage of capacitive switch and 17.5 % in device area has also been observed. The proposed design can be used as a building block for multiple throw switches and switch matrices for the future reconfigurable RF front end applications.

A novel reconfigurable variable gain amplifier for a multi-mode multi-band receiver

This paper presents a novel approach for designing a reconfigurable variable gain amplifier (VGA) for the multi-mode multi-band receiver system RF front-end applications. The configuration, which is comprised of gain circuits, control circuit, DC offset cancellation circuit and mode switch circuit is proposed to save die area and power consumption with the function of multi-mode and multi-band through reusing. The VGA is realized in 0.18 μm CMOS technology with 1.8 V power supply voltage providing a gain tuning range from 5 to 87 dB when the control voltage varies from 0 to 1.8 V. The 3 dB bandwidth is about 80 MHz for all levels of control voltage (all gains). Also, the DC offset cancellation circuit can effectively suppress DC offset to a value of less than 40 mV at the output regardless of the input. The overall power consumption is less than 3 mA, and die area is 705 × 100 μm2.

Broadband high-efficiency circularly polarized active antenna and array for RF front-end application

This paper presents a broadband high-efficiency circularly polarized (CP) active integrated antenna, and a broadband CP active array at 2 GHz. To realize the broadband CP antenna, a circular patch is aperture coupled by crossed slots in the ground plane, which are fed by an L-shaped microstrip feed line below the ground. The antenna is designed to serve the functions of both a radiator and a harmonics-terminated load for class-E high-efficiency power-amplifier (PA) integration. The broadband CP active antenna is realized by directly integrating the broadband CP antenna with the class-E PA. It achieves a 9% bandwidth (1.84-2.01 GHz) for axial ratio (AR) below 3 dB, and a 12% bandwidth for power-added efficiency (PAE) over 60%. To form the broadband CP active array, four active antenna elements are sequentially rotated, and each element is directly integrated with broadband class-E PA. A low-cost printed-circuit-board technology is employed in fabrication and a pseudomorphic high electron-mobility transistor is used. A peak drain efficiency of 71.5% for the class-E amplifier is measured at 1.95 GHz. The active array achieves a peak-effective radiated power of 39.7 dBm, and PAE is over 50% within a 22.6% bandwidth (1.72-2.16 GHz). The AR is below 3 dB over a 27% bandwidth (1.72-2.26 GHz).

RECENT PROGRESS ON GaN-BASED ELECTRON DEVICES

We present results of some novel AlGaN/GaN heterojunction field-effect transistors (HFETs) specifically developed for RF front-end and power applications. To reduce the parasitic resistance, two unique techniques: selective Si doping into contact area and a superlattice (SL) cap structure, are developed. With the selective Si doping method, a transistor with an on-state resistance as low as 1.86 Ω·mm and a Tx/Rx switch IC with very low insertion loss (0.26 dB) and very high power handling capability (P1dB over 40 dBm) were obtained. With the SL cap HFETs, an ultra low source resistance of 0.4 Ω·mm was achieved and excellent DC and RF performances were demonstrated. The typical characteristics of these HFETs are: maximum transconductance of over 400 mS/mm, maximum drain current of 1.2 A/mm, cut-off frequency of 60 GHz, maximum oscillation frequency of 140 GHz, and a very low noise figure of 0.7 dB with 15 dB gain at 12 GHz. For power applications, in order to significantly reduce fabrication cost, we fabricated the AlGaN/GaN HFET on a conductive Si substrate with a source-via grounding (SVG) structure. The device has a very low on-state sheet resistance of 1.9 mΩ·cm2, a high off-state breakdown voltage of 350 V, and a current handling capability of 150 A. In addition, a sub-nano second switching response with t r of 98 ps and t f of 96 ps with a current density as high as 2.0 kA/cm2 is demonstrated for the first time.

A 5.2 GHz low-voltage low-noise amplifier with 0.35 μm CMOS technology

A low-voltage CMOS low-noise amplifier (LNA) architecture is presented. We have used a TSMC 0.35 µm CMOS high-frequency model to design a fully integrated 1 V, 5.2 GHz two-stage CMOS low-noise amplifier for RF front-end applications. No off-chip element is needed and a conventional common-source with feedback technology is used in this circuit. The first stage of the LNA is the common-source with feedback structure and the output stage is a buffer which increases the gain somewhat. An interstage negative-impedance circuit is added between the two stages of the LNA to further enhance the overall gain and thus upgrade its performance. Mainly because of the finite Q of the inductor, the negative-impedance circuit used in this interstage can cancel the losses in the first-stage inductor load. The input and output matching network is matched to approximately 50 Ω. The simulation results show that the amplifier provides a gain of 9.48 dB, a noise figure of 4.08 dB, and draws 13.4 mW from a 1 V supply. The S11 and S22 are both lower than −15 dB.

Multifunctional Microstrip Transmission Lines Integrated With Defected Ground Structure for RF Front-End Application

This paper presents multifunctional microstrip transmission lines for designing a high port-isolation dual-frequency orthogonally polarized rectangular patch antenna and the antenna-integrated power amplifier. The proposed lines were realized through the integration of defected ground structures (DGSs) with conventional microstrip lines. A spiral-shaped DGS-integrated microstrip line enhances the port isolation of the antenna, while feeding the 2.0-GHz excitation to the antenna and filtering out the 2.5-GHz receiving signal from the other port. High-order harmonic signal suppression of the power amplifier at the 2.5-GHz port was accomplished by the dumbbell-shaped DGS, thereby improving the efficiency of the amplifier. Measurements show an improvement of 20 dB in port isolation and 3% in power-added efficiency relative to an identical RF front-end, but integrated with a conventional patch antenna. An image impedance of the DGS-integrated microstrip lines can be controlled by the integrated DGS geometries. Relatively high-impedances lines, i.e., 150 and 100 /spl Omega/, are effectively implemented using microstrip lines with 75- and 50-/spl Omega/ linewidths by incorporating the spiral- and dumbbell-shaped DGSs, respectively.

AlGaN/GaN HFET power amplifier integrated with microstrip antenna for RF front-end applications

A high-efficiency and compact AlGaN/GaN heterojunction field-effect transistor (HFET) power amplifier integrated with a microstrip antenna at 7.25 GHz is presented for RF front-end circuit applications. A microstrip circular sector antenna is employed as both a radiator and frequency-dependent output load. Higher order harmonics from the HFET in nonlinear operation are reactively terminated because of the harmonic termination characteristic of the antenna. Based on the optimum load impedance measured by a load-pull measurement setup, the AlGaN/GaN HFET power amplifier has been designed and fabricated at 7.25 GHz using the active integrated antenna concept. In this design approach, the measured antenna impedance is directly transformed to the optimum load impedance for maximum efficiency. The power amplifier with 1-mm gate periphery shows 42% peak power-added efficiency and 30.3-dBm saturated output power with a linear gain of 8 dB, which is in reasonably good agreement with measured discrete HFET load-pull data. Due to the antenna's characteristics, better than 30-dB harmonic suppression has been achieved at both the second and third harmonic frequencies in both the E- and H-planes. To the authors' best knowledge, this is the first demonstration of a high-frequency AlGaN/GaN HFET power amplifier integrated with an antenna.

The design of a 2-V 900-MHz CMOS bandpass amplifier

A 900 MHz low-power CMOS bandpass amplifier suitable for the applications of RF front-end in wireless communication receivers is proposed and analyzed. In this design, the temperature compensation circuit is used to stabilize the amplifier gain so that the overall amplifier has a good temperature stability. Moreover, the compact tunable positive-feedback circuit is connected to the integrated spiral inductor to generate the negative resistance and enhance its Q value. The simple diode varactor circuit is adopted for center-frequency tuning. These two improved circuits can reduce the power dissipation of the amplifier. An experimental chip fabricated by 0.5 μm double-poly-double-metal CMOS technology occupies a chip area of 500 \times 500 \mu {\rm m}^2; chip area. The measured results have verified the performance of the fabricated CMOS bandpass amplifier. Under a 2-V supply voltage, the measured quality factor is tunable between 4.5 and 50 and the tunable frequency range is between 845 MHz and 915 MHz. At Q = 30, the measured S_{21} is 20 dB whereas the noise figure is 5.2 dB in the passband. The gain variation is less than 4 dB in the range of 0–80°C. The dc power dissipation is 35 mW. Suitable amplifier gain, low power dissipation, and good temperature stability make the proposed bandpass amplifier quite feasible in RF front-end applications.

A 2.7-V 900-MHz CMOS LNA and mixer

A CMOS low-noise amplifier (LNA) and a mixer for RF front-end applications are described. A current reuse technique is described that increases amplifier transconductance for the LNA and mixer without increasing power dissipation, compared to standard topologies. At 900 MHz, the LNA minimum noise figure (NF) is 1.9 dB, input third-order intercept point (IIP3) is -3.2 dBm and forward gain is 15.6 dB. With a 1-GHz local oscillator (LO) and a 900-MHz RF input, the mixer minimum double sideband noise figure (DSB NF) is 5.8 dB, IIP3 is -4.1 dBm, and power conversion gain is 8.8 dB. The LNA and mixer, respectively, consume 20 mW and 7 mW from a 2.7 V power supply. The active areas of the LNA and mixer are 0.7 mm/spl times/0.4 mm and 0.7 mm/spl times/0.2 mm, respectively. The prototypes were fabricated in a 0.5-/spl mu/m CMOS process.