RF ASIC Research Articles

Analysis of Deep Level and Oxide Interface Defects Using 100V HF Schottky Diodes and MOS CV for Silicon and 4H SiC HV MOSFETs, Advanced Power Electronics, and RF ASIC

AbstractIn this paper we report high voltage MOS and Schottky Diode CV techniques for silicon and SiC power devices. 4H Silicon carbide is a wide bandgap semiconductor suitable for high voltage power electronics and RF applications due to high avalanche breakdown critical electric field, and thermal conductivity. The performance of various power devices, which may include MOSFET and Static Induction Transistor (SIT), can be affected by the deep level traps in the substrate and the oxide interfacial defects. We have characterized deep level trap (High Voltage Schottky Diode HF CV) and oxide interface trap densities (High Voltage HF MOS CV), measured the device channel doping profile for both 4H SiC and silicon, gate metal workfunction, and simulated the effects on DC/AC performance.

Design of a High Dynamic-Range RF ASIC for Anti-jamming GNSS Receiver

ABSTRACT Global Positioning System (GPS) is used in various fields such as communications systems, transportation systems, e-commerce, power plant systems, and up to various military weapons systems recently. However, GPS receiver is vulnerable to jamming signals as the GPS signals come from the satellites located at approximately 20,000 km above the earth. For this reason, various anti-jamming techniques have been developed for military application systems especially and it is also required for commercial application systems nowadays. In this paper, we proposed a dual-channel Global Navigation Satellite System (GNSS) RF ASIC for digital pre-correlation anti-jam technique. It not only covers all GNSS frequency bands, but is integrated low-gain/attenuation mode in low-noise amplifier (LNA) without influencing in/out matching and 14-bit analog-digital converter (ADC) to have a high dynamic range. With the aid of digital processing, jamming to signal ratio is improved to 77 dB from 42 dB with proposed receiver. RF ASIC for anti-jam is fabricated on a 0.18-μm complementary metal-oxide semiconductor (CMOS) technology and consumes 1.16 W with 2.1 V (low-dropout; LDO) power supply. And the performance is evaluated by a kind of test hardware using the designed RF ASIC.

UWB 병사통신 단말기의 구현

In this paper, we present the implementation result of an UWB terminal for mobile tactical networks. Considering the major characteristics of the terminals of tactical networks, i) targeting voice service, ii) pedestrian users, and iii) demanding high network fidelity, we designed all protocol layers from physical layer to applications layer. The designed terminal is implemented in forms of software and hardware with RF ASIC, FPGA, DSP, and GPP. The functionality of the implemented terminal is validated by successfully performing 1 to 1 and multi-hop voice communication test.

Signal generators add feature now required by many RF ASICs and ICs

Signal generators add feature now required by many RF ASICs and ICs