In quantum computers, all the heavy computations are done through quantum processors. ALU is one of the most significant parts of every processor responsible for performing logical operations and primary binary operations. All of the arithmetic computations in ALU utilize adder/subtractor to produce the expected result. Fault-tolerant circuit designs have found increasing application in quantum computers regarding the noise sensitivity of qubits and the faulty environment in which they operate. Additionally, reversible quantum circuits can prevent heat circulation and information lost throughout the high-rate binary calculations. The primary subject is the development of digital reversible fault-tolerant quantum circuits with higher performance and more efficiency regarding the number of inputs and outputs employed by quantum gates, depth, and delay. Full adders and subtractors are highly significant in different parts of quantum digital circuits and are used widely in multipliers, dividers, ALUs, and floating-point operations. In this paper, applying the parity-preserving method and the properties of Boolean algebra two novel reversible fault-tolerant designs are proposed that can detect every single or the odd number of errors. Also, both proposed designs are capable to perform addition and subtraction operations by changing the control signal(ctr). Our offered designs can reduce energy loss in the form of emitted heat in circuits, reduce the cost of building quantum circuits, reduce computation time, and detect errors in case of happen. Furthermore, comprehensive simulations for each possible combination of inputs and corresponding outputs are done to prove the full functionality and accurate performance of the proposed designs.